#
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# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#
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#include <AsmMacroIoLib.h>
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#include <Library/ArmLib.h>
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#include <Chipset/ArmCortexA9.h>
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ASM_FUNC(ArmPlatformPeiBootAction)
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bx lr
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# IN None
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# OUT r0 = SCU Base Address
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ASM_FUNC(ArmGetScuBaseAddress)
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# Read Configuration Base Address Register. ArmCBar cannot be called to get
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# the Configuration BAR as a stack is not necessary setup. The SCU is at the
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# offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx lr
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//UINTN
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//ArmPlatformGetPrimaryCoreMpId (
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// VOID
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// );
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ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
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MOV32 (r0, FixedPcdGet32 (PcdArmPrimaryCore))
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bx lr
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# IN None
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# OUT r0 = number of cores present in the system
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ASM_FUNC(ArmGetCpuCountPerCluster)
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stmfd SP!, {r1-r2}
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# Read CP15 MIDR
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mrc p15, 0, r1, c0, c0, 0
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# Check if the CPU is A15
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mov r1, r1, LSR #4
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MOV32 (r0, ARM_CPU_TYPE_MASK)
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and r1, r1, r0
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MOV32 (r0, ARM_CPU_TYPE_A15)
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cmp r1, r0
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beq _Read_cp15_reg
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_CPU_is_not_A15:
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mov r2, lr @ Save link register
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bl ArmGetScuBaseAddress @ Read SCU Base Address
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mov lr, r2 @ Restore link register val
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ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count
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b _Return
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_Read_cp15_reg:
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mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count
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lsr r0, #24
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_Return:
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and r0, r0, #3
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# Add '1' to the number of CPU on the Cluster
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add r0, r0, #1
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ldmfd SP!, {r1-r2}
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bx lr
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//UINTN
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//ArmPlatformIsPrimaryCore (
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// IN UINTN MpId
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// );
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ASM_FUNC(ArmPlatformIsPrimaryCore)
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MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
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and r0, r0, r1
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MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCore))
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cmp r0, r1
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moveq r0, #1
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movne r0, #0
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bx lr
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//UINTN
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//ArmPlatformGetCorePosition (
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// IN UINTN MpId
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// );
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ASM_FUNC(ArmPlatformGetCorePosition)
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and r1, r0, #ARM_CORE_MASK
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and r0, r0, #ARM_CLUSTER_MASK
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add r0, r1, r0, LSR #7
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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