/** @file
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* Header defining Versatile Express constants (Base addresses, sizes, flags)
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*
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* Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __ARM_VEXPRESS_H__
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#define __ARM_VEXPRESS_H__
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#include <VExpressMotherBoard.h>
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/***********************************************************************************
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// Platform Memory Map
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************************************************************************************/
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// Can be NOR0, NOR1, DRAM
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#define ARM_VE_REMAP_BASE 0x00000000
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#define ARM_VE_REMAP_SZ SIZE_64MB
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// Motherboard Peripheral and On-chip peripheral
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#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
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// NOR Flash 1
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// There is typo in the reference manual for the Base address of NOR Flash 1
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#define ARM_VE_SMB_NOR0_BASE 0x08000000
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#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
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// NOR Flash 2
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#define ARM_VE_SMB_NOR1_BASE 0x0C000000
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#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
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// SRAM
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#define ARM_VE_SMB_SRAM_BASE 0x2E000000
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#define ARM_VE_SMB_SRAM_SZ SIZE_64KB
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// USB, Ethernet, VRAM
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#define ARM_VE_SMB_PERIPH_BASE 0x18800000
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#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB)
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#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000
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#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE 0x800000
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// DRAM
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#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)
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#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)
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// This can be any value since we only support motherboard PL111
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#define LCD_VRAM_CORE_TILE_BASE 0x00000000
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// On-chip peripherals (Snoop Control Unit etc...)
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#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000
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// Note: The TRM says not all the peripherals are implemented
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#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB
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// External AXI between daughterboards (Logic Tile)
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#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled
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#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */
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/***********************************************************************************
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// Memory-mapped peripherals
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************************************************************************************/
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// SP810 Controller
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#undef SP810_CTRL_BASE
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#define SP810_CTRL_BASE 0x1C020000
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// PL111 Colour LCD Controller
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#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
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#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
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#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
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#define SBSA_WATCHDOG_BASE 0x2a440000
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#define SBSA_WATCHDOG_SIZE (2 * SIZE_64KB)
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// SMMUv3 - FVP RevC
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#define FVP_REVC_SMMUV3_BASE 0x2B400000
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#define FVP_REVC_SMMUV3_SIZE SIZE_1MB
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#endif
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