/** @file
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* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform
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*
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* This file describes the topological structure of the processor block on the
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* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The RD-V1
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* quad-chip platform is composed of four identical chips connected over cache
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* coherent interconnect. Each of the chip on the platform includes four single
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* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
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* cache and 1MB L2 cache. The platform also includes a system level cache of
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* 16MB per chip.
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*
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* Copyright (c) 2021, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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* @par Specification Reference:
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* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
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**/
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#include <IndustryStandard/Acpi.h>
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#include <Library/AcpiLib.h>
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#include <Library/ArmLib.h>
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#include <Library/PcdLib.h>
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#include "SgiPlatform.h"
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#include "SgiAcpiHeader.h"
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#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
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/** Define helper macro for populating processor core information.
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@param [in] PackageId Package instance number.
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@param [in] ClusterId Cluster instance number.
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@param [in] CpuId CPU instance number.
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**/
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#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
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{ \
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/* Parameters for CPU Core */ \
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EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
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OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
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PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
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OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
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Package[PackageId].Cluster[ClusterId]), /* Parent */ \
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((PackageId << 2) | ClusterId), /* ACPI Id */ \
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2 /* Num of private resource */ \
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), \
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\
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/* Offsets of the private resources */ \
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{ \
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OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
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Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), \
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OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
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Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) \
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}, \
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\
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/* L1 data cache parameters */ \
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EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
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PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
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OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
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Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
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/* Next level of cache */ \
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SIZE_64KB, /* Size */ \
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256, /* Num of sets */ \
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4, /* Associativity */ \
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PPTT_DATA_CACHE_ATTR, /* Attributes */ \
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64 /* Line size */ \
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), \
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\
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/* L1 instruction cache parameters */ \
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EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
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PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
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OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
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Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
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/* Next level of cache */ \
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SIZE_64KB, /* Size */ \
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256, /* Num of sets */ \
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4, /* Associativity */ \
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PPTT_INST_CACHE_ATTR, /* Attributes */ \
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64 /* Line size */ \
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), \
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\
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/* L2 cache parameters */ \
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EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
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PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
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0, /* Next level of cache */ \
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SIZE_1MB, /* Size */ \
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2048, /* Num of sets */ \
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8, /* Associativity */ \
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PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
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64 /* Line size */ \
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), \
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}
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/** Define helper macro for populating processor container information.
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@param [in] PackageId Package instance number.
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@param [in] ClusterId Cluster instance number.
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**/
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#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
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{ \
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/* Parameters for Cluster */ \
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EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
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OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
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PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
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OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
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Package[PackageId]), /* Parent */ \
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((PackageId << 2) | ClusterId), /* ACPI Id */ \
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0 /* Num of private resource */ \
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), \
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\
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/* Initialize child core */ \
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{ \
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PPTT_CORE_INIT (PackageId, ClusterId, 0) \
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} \
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}
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/** Define helper macro for populating SoC package information.
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@param [in] PackageId Package instance number.
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**/
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#define PPTT_PACKAGE_INIT(PackageId) \
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{ \
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EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
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OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ \
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PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
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0, /* Parent */ \
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0, /* ACPI Id */ \
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1 /* Num of private resource */ \
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), \
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\
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/* Offsets of the private resources */ \
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OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
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Package[PackageId].Slc), \
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\
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EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
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PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
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0, /* Next level of cache */ \
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SIZE_16MB, /* Size */ \
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16384, /* Num of sets */ \
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16, /* Associativity */ \
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PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
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64 /* Line size */ \
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), \
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\
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{ \
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PPTT_CLUSTER_INIT (PackageId, 0), \
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PPTT_CLUSTER_INIT (PackageId, 1), \
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PPTT_CLUSTER_INIT (PackageId, 2), \
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PPTT_CLUSTER_INIT (PackageId, 3), \
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} \
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}
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#pragma pack(1)
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/*
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* Processor Properties Topology Table
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*/
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typedef struct {
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EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
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RD_PPTT_SLC_PACKAGE Package[CHIP_COUNT];
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} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
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#pragma pack ()
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STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
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{
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ARM_ACPI_HEADER (
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EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
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EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
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EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
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)
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},
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{
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PPTT_PACKAGE_INIT (0),
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PPTT_PACKAGE_INIT (1),
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PPTT_PACKAGE_INIT (2),
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PPTT_PACKAGE_INIT (3)
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}
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};
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/*
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* Reference the table being generated to prevent the optimizer from removing
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* the data structure from the executable
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*/
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VOID* CONST ReferenceAcpiTable = &Pptt;
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