/** @file
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* Multiple APIC Description Table (MADT)
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*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include "SgiPlatform.h"
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#include "SgiAcpiHeader.h"
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#include <Library/AcpiLib.h>
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#include <Library/ArmLib.h>
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#include <Library/PcdLib.h>
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#include <IndustryStandard/Acpi.h>
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#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
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FixedPcdGet32 (PcdCoreCount))
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#define CHIP_CNT (FixedPcdGet32 (PcdChipCount))
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// Multiple APIC Description Table
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#pragma pack (1)
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typedef struct {
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EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
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EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT];
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EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
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EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CHIP_CNT];
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} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
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#pragma pack ()
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STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
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{
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ARM_ACPI_HEADER (
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EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
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EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
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EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
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),
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// MADT specific fields
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0, // LocalApicAddress
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0 // Flags
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},
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{
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// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
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// PmuIrq, GicBase, GicVBase,
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// GicHBase, GsivId, GicRBase,
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// Efficiency)
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// Note: The GIC Structure of the primary CPU must be the first entry
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// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
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// Chip - 0 CPUs
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0
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0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1
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0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2
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0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-3
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0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-4
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0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-5
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0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-6
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0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-7
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0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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// Chip - 1 CPUs
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-8
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0, 8, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-9
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0, 9, GET_MPID(0x01000000ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-10
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0, 10, GET_MPID(0x01000000ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-11
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0, 11, GET_MPID(0x01000000ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-12
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0, 12, GET_MPID(0x01000100ULL, 0x00ULL), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-13
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0, 13, GET_MPID(0x01000100ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-14
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0, 14, GET_MPID(0x01000100ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
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EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-15
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0, 15, GET_MPID(0x01000100ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
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FixedPcdGet32 (PcdGicDistributorBase),
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0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */)
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},
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// GIC Distributor Entry
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EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
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0, 3),
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{
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// GIC Redistributor for Chip 0
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EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
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SIZE_1MB),
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// GIC Redistributor for Chip 1
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EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase)
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+ SGI_REMOTE_CHIP_MEM_OFFSET(1),
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SIZE_1MB)
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}
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};
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//
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// Reference the table being generated to prevent the optimizer from removing
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// the data structure from the executable
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//
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VOID* CONST ReferenceAcpiTable = &Madt;
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