/** @file
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*
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* Copyright (c) 2013-2017, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __ARM_JUNO_H__
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#define __ARM_JUNO_H__
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//#include <VExpressMotherBoard.h>
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/***********************************************************************************
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// Platform Memory Map
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************************************************************************************/
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// Motherboard Peripheral and On-chip peripheral
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#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
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#define ARM_VE_BOARD_SYS_ID 0x0000
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#define ARM_VE_BOARD_SYS_PCIE_GBE_L 0x0074
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#define ARM_VE_BOARD_SYS_PCIE_GBE_H 0x0078
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#define ARM_VE_BOARD_SYS_ID_REV(word) ((word >> 28) & 0xff)
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// NOR Flash 0
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#define ARM_VE_SMB_NOR0_BASE 0x08000000
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#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
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// Off-Chip peripherals (USB, Ethernet, VRAM)
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#define ARM_VE_SMB_PERIPH_BASE 0x18000000
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#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_2MB)
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// On-Chip non-secure ROM
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#define ARM_JUNO_NON_SECURE_ROM_BASE 0x1F000000
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#define ARM_JUNO_NON_SECURE_ROM_SZ SIZE_16MB
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// On-Chip Peripherals
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#define ARM_JUNO_PERIPHERALS_BASE 0x20000000
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#define ARM_JUNO_PERIPHERALS_SZ 0x0E000000
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// PCIe MSI address window
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#define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c0000
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#define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB
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// PCIe MSI to SPI mapping range
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#define ARM_JUNO_GIV2M_MSI_SPI_BASE 224
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#define ARM_JUNO_GIV2M_MSI_SPI_COUNT 127 //TRM says last SPI is 351, 351-224=127
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// On-Chip non-secure SRAM
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#define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000
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#define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB
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// SOC peripherals (HDLCD, UART, I2C, I2S, USB, SMC-PL354, etc)
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#define ARM_JUNO_SOC_PERIPHERALS_BASE 0x7FF50000
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#define ARM_JUNO_SOC_PERIPHERALS_SZ (SIZE_64KB * 9)
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// 6GB of DRAM from the 64bit address space
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#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE 0x0880000000
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#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ (SIZE_2GB + SIZE_4GB)
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//
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// ACPI table information used to initialize tables.
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//
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#define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long
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#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','R','M','-','J','U','N','O') // OEM table id 8 bytes long
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#define EFI_ACPI_ARM_OEM_REVISION 0x20140727
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#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
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#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
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// A macro to initialise the common header part of EFI ACPI tables as defined by
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// EFI_ACPI_DESCRIPTION_HEADER structure.
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#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
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Signature, /* UINT32 Signature */ \
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sizeof (Type), /* UINT32 Length */ \
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Revision, /* UINT8 Revision */ \
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0, /* UINT8 Checksum */ \
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{ EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
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EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
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EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
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EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
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EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
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}
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//
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// Hardware platform identifiers
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//
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#define JUNO_REVISION_PROTOTYPE 0
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#define JUNO_REVISION_R0 1
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#define JUNO_REVISION_R1 2
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#define JUNO_REVISION_R2 3
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#define JUNO_REVISION_UKNOWN 0xFF
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//
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// We detect whether we are running on a Juno r0, r1 or r2
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// board at runtime by checking the value of board SYS_ID
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//
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#define GetJunoRevision(JunoRevision) \
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{ \
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UINT32 SysId; \
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SysId = MmioRead32 (ARM_VE_BOARD_PERIPH_BASE+ARM_VE_BOARD_SYS_ID); \
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JunoRevision = ARM_VE_BOARD_SYS_ID_REV( SysId ); \
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}
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// Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest
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//#define ARM_JUNO_ACPI_5_0
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//
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// Address of the system registers that contain the MAC address
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// assigned to the PCI Gigabyte Ethernet device.
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//
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#define ARM_JUNO_SYS_PCIGBE_L (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_L)
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#define ARM_JUNO_SYS_PCIGBE_H (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_H)
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/***********************************************************************************
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// Motherboard memory-mapped peripherals
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************************************************************************************/
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// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
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#define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00000)
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#define ARM_VE_SYS_SW_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00004)
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#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)
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#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
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#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
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#define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)
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#define ARM_VE_SYS_CFGSWR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00058)
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#define ARM_VE_SYS_MISC (ARM_VE_BOARD_PERIPH_BASE + 0x00060)
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#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
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#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
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#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
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#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
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#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
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//
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// Sites where the peripheral is fitted
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//
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#define ARM_VE_UNSUPPORTED ~0
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#define ARM_VE_MOTHERBOARD_SITE 0
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#define ARM_VE_DAUGHTERBOARD_1_SITE 1
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#define ARM_VE_DAUGHTERBOARD_2_SITE 2
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#define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))
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//
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// System Configuration Control Functions
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//
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#define SYS_CFG_OSC 1
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#define SYS_CFG_VOLT 2
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#define SYS_CFG_AMP 3
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#define SYS_CFG_TEMP 4
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#define SYS_CFG_RESET 5
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#define SYS_CFG_SCC 6
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#define SYS_CFG_MUXFPGA 7
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#define SYS_CFG_SHUTDOWN 8
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#define SYS_CFG_REBOOT 9
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#define SYS_CFG_DVIMODE 11
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#define SYS_CFG_POWER 12
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// Oscillator for Site 1
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#define SYS_CFG_OSC_SITE1 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE, \
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SYS_CFG_OSC)
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// Oscillator for Site 2
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#define SYS_CFG_OSC_SITE2 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE, \
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SYS_CFG_OSC)
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// Can not access the battery backed-up hardware clock on the
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// Versatile Express motherboard
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#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)
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#endif
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