/** @file
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Usb3 Debug Port library instance
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Copyright (c) 2013 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <PiDxe.h>
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#include <Library/SerialPortLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Library/PciLib.h>
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#include <Library/PcdLib.h>
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#include <Library/TimerLib.h>
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#include <Library/Usb3DebugPortParamLib.h>
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#include <Protocol/SmmBase2.h>
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#include <Protocol/SmmAccess2.h>
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#include "Usb3DebugPortLibInternal.h"
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extern EFI_SMRAM_DESCRIPTOR mSmramCheckRanges[MAX_SMRAM_RANGE];
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extern UINTN mSmramCheckRangeCount;
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extern BOOLEAN mUsb3InSmm;
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extern UINT64 mUsb3MmioSize;
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extern BOOLEAN mUsb3GetCapSuccess;
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GUID gUsb3DbgGuid = USB3_DBG_GUID;
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USB3_DEBUG_PORT_CONTROLLER mUsb3DebugPort;
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USB3_DEBUG_PORT_INSTANCE *mUsb3Instance = NULL;
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/**
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Return XHCI MMIO base address.
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**/
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EFI_PHYSICAL_ADDRESS
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GetXhciBaseAddress (
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VOID
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)
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{
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UINT8 Bus;
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UINT8 Device;
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UINT8 Function;
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EFI_PHYSICAL_ADDRESS Address;
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UINT32 Low;
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UINT32 High;
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if (mUsb3DebugPort.Controller == 0) {
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mUsb3DebugPort.Controller = GetUsb3DebugPortController();
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}
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Bus = mUsb3DebugPort.PciAddress.Bus;
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Device = mUsb3DebugPort.PciAddress.Device;
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Function = mUsb3DebugPort.PciAddress.Function;
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Low = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET));
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High = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));
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Address = (EFI_PHYSICAL_ADDRESS) (LShiftU64 ((UINT64) High, 32) | Low);
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//
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// Mask other parts which are not part of base address
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//
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Address &= XHCI_BASE_ADDRESS_64_BIT_MASK;
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return Address;
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}
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/**
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Return XHCI debug instance address.
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**/
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USB3_DEBUG_PORT_INSTANCE *
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GetUsb3DebugPortInstance (
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VOID
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)
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{
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USB3_DEBUG_PORT_INSTANCE *Instance;
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EFI_PHYSICAL_ADDRESS XhcMmioBase;
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UINT64 CapabilityPointer;
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UINT32 Capability;
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BOOLEAN Flag;
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UINT8 Bus;
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UINT8 Device;
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UINT8 Function;
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UINT16 Command;
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USB3_DEBUG_PORT_CONTROLLER UsbDebugPort;
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Instance = NULL;
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XhcMmioBase = GetXhciBaseAddress ();
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if ((XhcMmioBase == 0) || (XhcMmioBase == XHCI_BASE_ADDRESS_64_BIT_MASK)) {
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return NULL;
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}
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if (mUsb3Instance != NULL) {
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FixUsb3InstanceResource (mUsb3Instance, XhcMmioBase);
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return mUsb3Instance;
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}
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Command = GetXhciPciCommand ();
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UsbDebugPort.Controller = GetUsb3DebugPortController();
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Bus = UsbDebugPort.PciAddress.Bus;
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Device = UsbDebugPort.PciAddress.Device;
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Function = UsbDebugPort.PciAddress.Function;
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//
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// Set Command Register
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//
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if ((Command & EFI_PCI_COMMAND_MEMORY_SPACE) == 0) {
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PciWrite16(PCI_LIB_ADDRESS(Bus, Device, Function, PCI_COMMAND_OFFSET), Command | EFI_PCI_COMMAND_MEMORY_SPACE);
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PciRead16(PCI_LIB_ADDRESS(Bus, Device, Function, PCI_COMMAND_OFFSET));
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}
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//
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// Calculate capability offset from HCCPARAMS [16:31], in 32-bit words
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//
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CapabilityPointer = XhcMmioBase + (MmioRead32 ((UINTN)(XhcMmioBase + XHC_HCCPARAMS_OFFSET)) >> 16) * 4;
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//
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// Search XHCI debug capability
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//
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Flag = FALSE;
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Capability = MmioRead32 ((UINTN)CapabilityPointer);
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while (TRUE) {
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if ((Capability & XHC_CAPABILITY_ID_MASK) == PCI_CAPABILITY_ID_DEBUG_PORT) {
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Flag = TRUE;
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break;
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}
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if ((((Capability & XHC_NEXT_CAPABILITY_MASK) >> 8) & XHC_CAPABILITY_ID_MASK) == 0) {
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//
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// Reach the end of list, quit
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//
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break;
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}
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CapabilityPointer += ((Capability & XHC_NEXT_CAPABILITY_MASK) >> 8) * 4;
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Capability = MmioRead32 ((UINTN)CapabilityPointer);
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}
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if (Flag) {
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Instance = (USB3_DEBUG_PORT_INSTANCE *)(UINTN) MmioRead32 ((UINTN) (CapabilityPointer + XHC_DC_DCDDI2));
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if (Instance != NULL) {
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FixUsb3InstanceResource (Instance, XhcMmioBase);
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}
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}
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//
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// Restore Command Register
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//
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PciWrite16(PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), Command);
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return Instance;
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}
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/**
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Initialize USB3 debug port.
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This method invokes various internal functions to facilitate
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detection and initialization of USB3 debug port.
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@retval RETURN_SUCCESS The USB3 debug port was initialized.
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**/
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RETURN_STATUS
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EFIAPI
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USB3Initialize (
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VOID
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)
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{
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//
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// Leave it empty, we assume PEI phase already do initialization
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//
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return RETURN_SUCCESS;
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}
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/**
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Initialize USB3 debug port.
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This method invokes various internal functions to facilitate
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detection and initialization of USB3 debug port.
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@retval RETURN_SUCCESS The serial device was initialized.
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**/
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RETURN_STATUS
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EFIAPI
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USB3InitializeReal (
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VOID
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)
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{
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USB3_DEBUG_PORT_INSTANCE UsbDbg;
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USB3_DEBUG_PORT_INSTANCE *Instance;
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EFI_PHYSICAL_ADDRESS Address;
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EFI_STATUS Status;
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if ((gST == NULL) || (gBS == NULL)) {
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//
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// gST and gBS have not been initialized yet
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//
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return EFI_DEVICE_ERROR;
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}
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Status = EfiGetSystemConfigurationTable (&gUsb3DbgGuid, (VOID **) &mUsb3Instance);
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if (!EFI_ERROR (Status)) {
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return RETURN_SUCCESS;
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}
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//
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// It is first time to run DXE instance, copy Instance from Hob to ACPINvs
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// NOTE: Hob is not ready at this time, so copy it from XHCI register.
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//
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Instance = GetUsb3DebugPortInstance ();
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if (Instance == NULL) {
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//
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// Initialize USB debug
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//
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SetMem (&UsbDbg, sizeof(UsbDbg), 0);
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DiscoverUsb3DebugPort (&UsbDbg);
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if (UsbDbg.DebugSupport) {
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InitializeUsb3DebugPort (&UsbDbg);
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}
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Instance = &UsbDbg;
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}
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Address = SIZE_4GB;
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Status = gBS->AllocatePages (
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AllocateMaxAddress,
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EfiACPIMemoryNVS,
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EFI_SIZE_TO_PAGES (sizeof (USB3_DEBUG_PORT_INSTANCE)),
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&Address
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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CopyMem (
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(VOID *)(UINTN)Address,
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Instance,
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sizeof (USB3_DEBUG_PORT_INSTANCE)
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);
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mUsb3Instance = (USB3_DEBUG_PORT_INSTANCE *)(UINTN)Address;
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Status = gBS->InstallConfigurationTable (&gUsb3DbgGuid, mUsb3Instance);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if (mUsb3Instance->DebugSupport) {
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SaveUsb3InstanceAddress (mUsb3Instance);
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}
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return RETURN_SUCCESS;
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}
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/**
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Calculate the size of XHCI MMIO space.
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@retval TURE The XHCI MMIO is in SMRAM ranges.
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@retval FALSE The XHCI MMIO is out of SMRAM ranges.
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**/
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UINT64
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CalculateMmioSize (
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VOID
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)
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{
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UINT8 Bus;
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UINT8 Device;
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UINT8 Function;
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UINT32 Value;
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UINT32 Mask;
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UINT64 MmioSize;
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UINT16 Command;
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USB3_DEBUG_PORT_CONTROLLER UsbDebugPort;
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EFI_PHYSICAL_ADDRESS XhcMmioBase;
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UsbDebugPort.Controller = GetUsb3DebugPortController();
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Bus = UsbDebugPort.PciAddress.Bus;
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Device = UsbDebugPort.PciAddress.Device;
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Function = UsbDebugPort.PciAddress.Function;
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Mask = 0xFFFFFFF0;
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MmioSize = 0;
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XhcMmioBase = GetXhciBaseAddress ();
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//
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// Disable MSE
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//
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Command = PciRead16 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_COMMAND_OFFSET));
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PciWrite16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), Command & ~(EFI_PCI_COMMAND_MEMORY_SPACE));
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//
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// Get Mmio Size
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//
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PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF);
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Value = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET));
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switch (Value & 0x07) {
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case 0x0:
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//
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// Memory space: anywhere in 32 bit address space
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//
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MmioSize = (~(Value & Mask)) + 1;
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break;
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case 0x4:
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//
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// Memory space: anywhere in 64 bit address space
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//
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MmioSize = Value & Mask;
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PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);
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Value = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));
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//
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// Fix the length to support some spefic 64 bit BAR
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//
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Value |= ((UINT32)(-1) << HighBitSet32 (Value));
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//
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// Calculate the size of 64bit bar
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//
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MmioSize |= LShiftU64 ((UINT64) Value, 32);
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MmioSize = (~(MmioSize)) + 1;
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break;
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default:
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//
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// Unknown BAR type
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//
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MmioSize = (~(Value & Mask)) + 1;
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break;
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};
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//
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// Restore MMIO address
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//
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PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), (UINT32)XhcMmioBase);
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PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), (UINT32) (XhcMmioBase >> 32));
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PciWrite16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), Command | EFI_PCI_COMMAND_MEMORY_SPACE);
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return MmioSize;
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}
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/**
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The constructor function initialize USB3 debug port.
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@param ImageHandle The firmware allocated handle for the EFI image.
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@param SystemTable A pointer to the EFI System Table.
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@retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
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**/
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EFI_STATUS
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EFIAPI
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Usb3DebugPortLibDxeConstructor (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_SMM_BASE2_PROTOCOL *SmmBase;
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EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
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UINTN Size;
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EFI_STATUS Status;
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//
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// Do real initialization here, because we need copy data from Hob to ACPINvs.
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// We must do it in constructor because it depends on UefiBootServicesTableLib.
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//
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if (FeaturePcdGet (PcdUsb3DebugFeatureEnable)) {
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USB3InitializeReal ();
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}
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mUsb3MmioSize = CalculateMmioSize ();
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if (gBS != NULL) {
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SmmBase = NULL;
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Status = gBS->LocateProtocol (&gEfiSmmBase2ProtocolGuid, NULL, (VOID **)&SmmBase);
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if (!EFI_ERROR (Status)) {
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SmmBase->InSmm(SmmBase, &mUsb3InSmm);
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}
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if (mUsb3InSmm) {
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//
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// Get SMRAM information
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//
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SmmAccess = NULL;
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Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);
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if (!EFI_ERROR (Status)) {
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Size = sizeof (mSmramCheckRanges);
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Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmramCheckRanges);
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if (!EFI_ERROR (Status)) {
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mSmramCheckRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
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}
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}
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}
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}
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return EFI_SUCCESS;
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}
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/**
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Allocate aligned memory for XHC's usage.
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@param BufferSize The size, in bytes, of the Buffer.
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@return A pointer to the allocated buffer or NULL if allocation fails.
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**/
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VOID*
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AllocateAlignBuffer (
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IN UINTN BufferSize
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)
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{
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VOID *Buf;
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EFI_PHYSICAL_ADDRESS Address;
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EFI_STATUS Status;
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Buf = NULL;
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if (gBS != NULL) {
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Address = 0xFFFFFFFF;
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Status = gBS->AllocatePages (
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AllocateMaxAddress,
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EfiACPIMemoryNVS,
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EFI_SIZE_TO_PAGES (BufferSize),
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&Address
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);
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if (!EFI_ERROR (Status)) {
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Buf = (VOID *)(UINTN)Address;
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}
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}
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return Buf;
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}
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/**
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Check whether AllocatePages in permanent memory is ready.
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@retval TRUE AllocatePages in permanent memory is ready.
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@retval FALSE AllocatePages in permanent memory is not ready.
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**/
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BOOLEAN
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IsAllocatePagesReady (
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VOID
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)
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{
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if (gBS != NULL) {
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return TRUE;
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}
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return FALSE;
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}
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