// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright SolidRun Ltd.
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*
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* Device tree for the CN9131 COM Express Type 7 board.
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*/
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#include "cn9130-cex7.dts"
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/ {
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model = "SolidRun CN9131 based COM Express type 7";
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compatible = "marvell,cn9131", "marvell,cn9130",
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"marvell,armada-ap807-quad", "marvell,armada-ap807";
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aliases {
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gpio3 = &cp1_gpio1;
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gpio4 = &cp1_gpio2;
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ethernet3 = &cp1_eth0;
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};
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cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
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compatible = "regulator-fixed";
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regulator-name = "cp1-xhci0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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};
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cp1_usb3_0_phy0: cp1_usb3_phy0 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp1_reg_usb3_vbus0>;
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};
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cp1_reg_usb3_vbus1: cp1_usb3_vbus@1 {
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compatible = "regulator-fixed";
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regulator-name = "cp1-xhci1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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};
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cp1_usb3_0_phy1: cp1_usb3_phy@1 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp1_reg_usb3_vbus1>;
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};
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cp1_sfp_eth0: sfp_eth0{
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compatible = "sff,sfp";
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i2c-bus = <&cp1_i2c1>;
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mod-def0-gpio = <&cp1_gpio2 18 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_sfp_present_pins>;
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status = "okay";
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};
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};
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/* Instantiate the first slave CP115 */
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#define CP11X_NAME cp1
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#define CP11X_BASE f4000000
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#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x2000000))
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#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
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#define CP11X_PCIE0_BASE f4600000
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#define CP11X_PCIE1_BASE f4620000
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#define CP11X_PCIE2_BASE f4640000
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#include "armada-cp115.dtsi"
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#undef CP11X_NAME
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#undef CP11X_BASE
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#undef CP11X_PCIEx_MEM_BASE
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#undef CP11X_PCIEx_MEM_SIZE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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#undef CP11X_PCIE2_BASE
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&cp1_crypto {
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status = "disabled";
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};
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&cp1_ethernet {
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status = "okay";
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};
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/* 5GE PHY0 */
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&cp1_eth0 {
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status = "okay";
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phy-mode = "5gbase-r";
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phys = <&cp1_comphy2 0>;
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phy = <&phy1>;
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sfp = <&cp1_sfp_eth0>;
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};
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&cp1_gpio1 {
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status = "okay";
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};
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&cp1_gpio2 {
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status = "okay";
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};
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&cp1_xmdio {
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status = "okay";
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pinctrl-0 = <&cp1_xmdio_pins>;
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phy1: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0>;
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};
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};
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&cp1_i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_i2c1_pins>;
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clock-frequency = <100000>;
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};
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/* PCIE X2 NVME */
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&cp1_pcie0 {
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pinctrl-names = "default";
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num-lanes = <2>;
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num-viewport = <8>;
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status = "okay";
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phys = <&cp1_comphy0 0
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&cp1_comphy1 0>;
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};
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/* SATA 1 */
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&cp1_sata0 {
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status = "okay";
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sata-port@1 {
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/* Generic PHY, providing serdes lanes */
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phys = <&cp1_comphy3 1>;
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};
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};
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/* PCIE X1 WIFI0 */
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&cp1_pcie1 {
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pinctrl-names = "default";
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num-lanes = <1>;
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num-viewport = <8>;
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status = "okay";
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phys = <&cp1_comphy4 1>;
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};
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/* PCIE X1 WIFI1 */
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&cp1_pcie2 {
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pinctrl-names = "default";
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num-lanes = <1>;
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num-viewport = <8>;
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status = "okay";
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phys = <&cp1_comphy5 2>;
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};
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/* PIN Definition */
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&cp1_syscon0 {
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cp1_pinctrl: pinctrl {
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compatible = "marvell,cp115-standalone-pinctrl";
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cp1_i2c1_pins: cp1-i2c-pins-1 {
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marvell,pins = "mpp35", "mpp36";
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marvell,function = "i2c1";
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};
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cp1_xmdio_pins: cp1_xmdio_pins-0 {
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marvell,pins = "mpp37", "mpp38";
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marvell,function = "xg";
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};
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cp1_sfp_present_pins: cp1_sfp_present_pins-0 {
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marvell,pins = "mpp50";
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marvell,function = "gpio";
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};
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};
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};
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&cp1_usb3_0 {
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status = "okay";
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sb-phy = <&cp1_usb3_0_phy0>;
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phy-names = "usb";
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};
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&cp1_usb3_1 {
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status = "okay";
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usb-phy = <&cp1_usb3_0_phy1>;
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phy-names = "usb";
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};
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