// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright SolidRun Ltd.
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*
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* Device tree for the CN9130 based COM Express type 7 board.
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*/
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#define GPIO_ACTIVE_HIGH 0
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#define GPIO_ACTIVE_LOW 1
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#include "cn9130.dtsi"
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/ {
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model = "SolidRun CN9130 based COM Express type 7";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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gpio1 = &cp0_gpio1;
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gpio2 = &cp0_gpio2;
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i2c0 = &cp0_i2c0;
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ethernet0 = &cp0_eth0; // SFP+ Port
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ethernet1 = &cp0_eth1; // RGMII
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ethernet2 = &cp0_eth2; // HS-SGMII
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spi1 = &cp0_spi0;
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spi2 = &cp0_spi1;
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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v_3_3: regulator-3-3v {
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compatible = "regulator-fixed";
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regulator-name = "v_3_3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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status = "okay";
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};
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ap0_reg_sd_vccq: ap0_sd_vccq@0 {
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compatible = "regulator-gpio";
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regulator-name = "ap0_sd_vccq";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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states = <1800000 0x1 3300000 0x0>;
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};
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cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
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compatible = "regulator-fixed";
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regulator-name = "cp0-xhci0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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};
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cp0_usb3_0_phy0: cp0_usb3_phy@0 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp0_reg_usb3_vbus0>;
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};
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cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
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compatible = "regulator-fixed";
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regulator-name = "cp0-xhci1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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};
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cp0_usb3_0_phy1: cp0_usb3_phy@1 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp0_reg_usb3_vbus1>;
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};
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cp0_reg_sd_vccq: cp0_sd_vccq@0 {
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compatible = "regulator-gpio";
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regulator-name = "cp0_sd_vccq";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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states = <1800000 0x1
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3300000 0x0>;
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};
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cp0_reg_sd_vcc: cp0_sd_vcc@0 {
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compatible = "regulator-fixed";
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regulator-name = "cp0_sd_vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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regulator-always-on;
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};
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cp0_sfp_eth0: sfp-eth@0 {
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compatible = "sff,sfp";
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i2c-bus = <&cp0_sfp_i2c>;
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mod-def0-gpio = <&cp0_gpio1 24 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sfp_present_pins>;
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};
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};
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&uart0 {
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status = "okay";
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};
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&cp0_uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_uart2_pins>;
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status = "okay";
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};
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/* on-board eMMC */
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&ap_sdhci0 {
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pinctrl-names = "default";
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bus-width = <8>;
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vqmmc-supply = <&ap0_reg_sd_vccq>;
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status = "okay";
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};
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&cp0_crypto {
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status = "disabled";
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};
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&cp0_ethernet {
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status = "okay";
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};
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/* SFP+ 10GE */
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&cp0_eth0 {
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status = "okay";
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phy-mode = "10gbase-kr";
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phys = <&cp0_comphy4 0>;
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managed = "in-band-status";
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sfp = <&cp0_sfp_eth0>;
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};
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/* RGMII 1GE */
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&cp0_eth1 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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&cp0_gpio1 {
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status = "okay";
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};
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&cp0_gpio2 {
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status = "okay";
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};
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/* Switch uplink */
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&cp0_eth2 {
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status = "okay";
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phy-mode = "2500base-x";
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phys = <&cp0_comphy5 2>;
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fixed-link {
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speed = <2500>;
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full-duplex;
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};
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};
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/* EEPROM */
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&cp0_i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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clock-frequency = <100000>;
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/* EEPROM */
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eeprom0: eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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pagesize = <0x20>;
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};
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};
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/* I2C Master */
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&cp0_i2c1 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c1_pins>;
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i2c-switch@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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clk_gen_i2c: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/*connected to clk generator*/
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};
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led_i2c: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* i2c_led connected to gpio expander on carrier according to com-ex type7 */
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};
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cp0_sfp_i2c: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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/*connected to sfp cp0_eth0*/
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};
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smbus: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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/* smbus connected to com-ex type7 connector */
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current_mon@40 {
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compatible = "ti,ina220";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40>;
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};
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};
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therm_i2c: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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fan-control-emc2301@2f {
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compatible = "smsc,emc2305";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2f>;
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fan@0 {
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reg = <0>;
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pwm-enable = <0>;
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fan-div = <4>;
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};
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};
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};
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};
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};
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&cp0_mdio {
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status = "okay";
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pinctrl-0 = <&cp0_ge_mdio_pins>;
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phy0: ethernet-phy@0 {
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marvell,reg-init = <3 16 0 0x1a4a>;
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reg = <0>;
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};
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switch0: switch0@4 {
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compatible = "marvell,mv88e6085";
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reg = <4>;
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pinctrl-names = "default";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan2";
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phy-handle = <&switch0phy0>;
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};
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port@2 {
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reg = <2>;
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label = "lan1";
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phy-handle = <&switch0phy1>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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phy-handle = <&switch0phy2>;
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};
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port@4 {
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reg = <4>;
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label = "lan3";
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phy-handle = <&switch0phy3>;
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <&cp0_eth2>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: switch0phy0@11 {
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reg = <0x11>;
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};
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switch0phy1: switch0phy1@12 {
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reg = <0x12>;
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};
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switch0phy2: switch0phy2@13 {
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reg = <0x13>;
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};
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switch0phy3: switch0phy3@14 {
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reg = <0x14>;
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};
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};
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};
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};
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/* PCIE X4 Slot */
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&cp0_pcie0 {
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status = "okay";
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num-lanes = <4>;
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num-viewport = <8>;
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy0 0
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&cp0_comphy1 0
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&cp0_comphy2 0
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&cp0_comphy3 0>;
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};
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/* PCIE X1 Slot */
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/*
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*&cp0_pcie2 {
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* status = "okay";
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* phys = <&cp0_comphy5 2>;
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* num-lanes = <1>;
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*};
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*/
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/* SD Card */
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&cp0_sdhci0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sdhci_pins
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&cp0_sdhci_cd_pins>;
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bus-width = <4>;
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cd-gpios = <&cp0_gpio2 24 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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vqmmc-supply = <&v_3_3>;
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vmmc-supply = <&v_3_3>;
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};
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&cp0_spi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_spi1_pins
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&cp0_spi1_cs1_pins>;
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reg = <0x700680 0x50>;
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spi-flash@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-max-frequency = <10000000>;
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};
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spi-flash@1 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "jedec,spi-nor";
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reg = <0x1>;
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/* On carrier MUX does not allow higher frequencies */
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spi-max-frequency = <10000000>;
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};
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};
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&cp0_syscon0 {
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cp0_pinctrl: pinctrl {
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compatible = "marvell,cp115-standalone-pinctrl";
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cp0_ge_mdio_pins: ge-mdio-pins {
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marvell,pins = "mpp40", "mpp41";
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marvell,function = "ge";
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};
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cp0_i2c0_pins: cp0-i2c-pins-0 {
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marvell,pins = "mpp37", "mpp38";
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marvell,function = "i2c0";
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};
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cp0_i2c1_pins: cp0-i2c-pins-1 {
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marvell,pins = "mpp35", "mpp36";
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marvell,function = "i2c1";
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};
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cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
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marvell,pins = "mpp0", "mpp1", "mpp2",
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"mpp3", "mpp4", "mpp5",
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"mpp6", "mpp7", "mpp8",
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"mpp9", "mpp10", "mpp11";
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marvell,function = "ge0";
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};
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cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
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marvell,pins = "mpp55";
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marvell,function = "sdio";
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};
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cp0_sdhci_pins: cp0-sdhi-pins-0 {
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marvell,pins = "mpp56", "mpp57", "mpp58",
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"mpp59", "mpp60", "mpp61";
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marvell,function = "sdio";
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};
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cp0_spi1_pins: cp0-spi-pins-1 {
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marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
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marvell,function = "spi1";
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};
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cp0_spi1_cs1_pins: cp0-spi-cs1-pins-1 {
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marvell,pins = "mpp12";
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marvell,function = "spi1";
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};
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cp0_sfp_present_pins: sfp-present-pins {
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marvell,pins = "mpp24";
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marvell,function = "gpio";
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};
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cp0_uart2_pins: uart22-pins {
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marvell,pins = "mpp50", "mpp51";
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marvell,function = "uart2";
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};
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};
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};
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&cp0_usb3_0 {
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status = "okay";
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usb-phy = <&cp0_usb3_0_phy0>;
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phy-names = "usb";
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};
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&cp0_usb3_1 {
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status = "okay";
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usb-phy = <&cp0_usb3_0_phy1>;
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phy-names = "usb";
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};
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