/* $NoKeywords */
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/**
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* @file
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*
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* AmdIscpDxeProtocol.h
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*
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* Contains Intra-SoC Communication DXE Protocol definitions.
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: FDK
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* @e sub-project: UEFI
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* @e version: $Revision: 337020 $ @e date: $Date: 2016-03-02 11:49:34 -0600 (Wed, 02 Mar 2016) $
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*
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*/
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/*****************************************************************************
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*
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* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
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*
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* This program and the accompanying materials are licensed and made available
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* under the terms and conditions of the BSD License which accompanies this
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* distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
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* IMPLIED.
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*
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***************************************************************************/
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#ifndef __AMD_ISCP_DXE_PROTOCOL__H_
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#define __AMD_ISCP_DXE_PROTOCOL__H_
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#include <Iscp.h>
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/*----------------------------------------------------------------------------------------
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* G U I D D E F I N I T I O N
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*----------------------------------------------------------------------------------------
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*/
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#define AMD_ISCP_DXE_PROTOCOL_GUID {\
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0x5c794c8, 0x6aef, 0x4450, 0x91, 0x78, 0xca, 0x70, 0x53, 0x75, 0xbd, 0x91 \
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}
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/*----------------------------------------------------------------------------------------
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* E X T E R N S
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*----------------------------------------------------------------------------------------
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*/
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extern EFI_GUID gAmdIscpDxeProtocolGuid;
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*----------------------------------------------------------------------------------------
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*/
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typedef struct _AMD_ISCP_DXE_PROTOCOL AMD_ISCP_DXE_PROTOCOL;
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/// HEST Notification type
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typedef enum {
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HEST_NOTIFY_POLLED = 0, ///< Polled
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HEST_NOTIFY_GPIO = 7, ///< GPIO-Signal
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} HEST_NOTIFY_TYPE;
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/// Trusted Firmware Generic Error Source structure
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typedef struct {
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UINT32 IscpVersion; ///< Version of BERT Region structure
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UINT8 SourceGUID[16]; ///< ACPI v6.0: Table 18-331 [Section Type]
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UINT64 ErrorStatusPhysAddr; ///< ACPI v6.0: Table 18-329 [Error Status Address]
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UINT32 ErrorStatusLength; ///< ACPI v6.0: Table 18-329 [Error Status Block Length]
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HEST_NOTIFY_TYPE NotificationType; ///< ACPI v6.0: Table 18-332 [Type]
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} ISCP_TFW_GENERIC_ERROR_SOURCE;
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/// CPU Core Reset Prototype
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_CPU_CORE_RESET) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure
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);
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_CPU_RETRIEVE_ID) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure
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);
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/// ISCP call to get MAC Address
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_GET_MAC_ADDRESS) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the Firmware MAC Address structure
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);
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/// ISCP call to set MAC Address
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_SET_MAC_ADDRESS) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the Firmware MAC Address structure
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);
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/// ISCP call to get Real-Time-Clock
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_GET_RTC) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock structure
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);
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/// ISCP call to set Real-Time-Clock
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_SET_RTC) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock structure
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);
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/// Update Firmware Volume Block into SPI from local memory
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_UPDATE_FV_BLOCK_DXE) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block
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IN OUT UINT8 *NvData, ///< Pointer to data being stored in FV Block
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IN CONST UINT32 NvSize ///< Size of data being stored FV Block
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);
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/// Load Firmware Volume Block from SPI into local memory
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_LOAD_FV_BLOCK_DXE) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block
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IN OUT UINT8 *NvData, ///< Pointer to data being stored in FV Block
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IN CONST UINT32 NvSize ///< Size of data being retrieved from FV Block
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);
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/// Erase Firmware Volume Block Prototype
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_ERASE_FV_BLOCK_DXE) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block
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IN CONST UINT32 NvSize ///< Size of data being erased
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);
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/// Update EEPROM Block from local memory prototype
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_UPDATE_EEPROM_BLOCK_DXE) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block
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IN OUT UINT8 *Data, ///< Pointer to data being stored in EEPROM Block
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IN CONST UINT32 Size ///< Size of data being stored EEPROM Block
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);
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/// Load EEPROM Block into local memory prototype
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_LOAD_EEPROM_BLOCK_DXE) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block
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IN OUT UINT8 *Data, ///< Pointer to data being stored in EEPROM Block
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IN CONST UINT32 Size ///< Size of data being retrieved from EEPROM Block
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);
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/// Erase EEPROM Block prototype
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_ERASE_EEPROM_BLOCK_DXE) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block
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IN CONST UINT32 Size ///< Size of data being erased
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);
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/// Issue ISCP Doorbell command
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_GET_BMC_IP_ADDRESS) (
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IN AMD_ISCP_DXE_PROTOCOL *This,
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IN OUT ISCP_BMC_IP_ADDRESS_INFO *BmcIpAddressInfo
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);
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/// Issue ISCP command to retrieve SMBIOS info
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_SMBIOS_INFO) (
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IN AMD_ISCP_DXE_PROTOCOL *This,
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IN OUT ISCP_SMBIOS_INFO *SmbiosInfo
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);
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/// Issue ISCP command to issue SoC shutdown command
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_SOC_SHUTDOWN) (
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IN AMD_ISCP_DXE_PROTOCOL *This
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);
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/// Issue ISCP command to issue SoC reset command
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_SOC_RESET) (
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IN AMD_ISCP_DXE_PROTOCOL *This
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);
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/// ISCP call to set Memory Set up Nodes
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_MEM_SETUP) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN OUT MEM_SETUP_VAR *SetupInfo ///< Pointer to the Firmware MAC Address structure
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);
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/// Issue Override Command
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_OVERRIDE_CMD) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN ISCP_OVERRIDE_CMD_INFO *OverrideCmdInfo ///< Pointer to the Overrride Command structure
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);
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/// Issue Sata1 get state
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_SATA1_GET) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN OUT ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to the SATA1 reset structure
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);
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/// Issue Sata1 set state
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_SATA1_SET) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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IN ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to the SATA1 reset structure
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);
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/// Issue BMC presence check
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_BMC_PRESENT) (
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IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
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OUT ISCP_BMC_PRESENCE_INFO *BmcPresenceInfo ///< Pointer to BMC presence structure
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);
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/// Register Boot Error Region
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_RETRIEVE_BERT_RECORD) (
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IN AMD_ISCP_DXE_PROTOCOL *This,
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IN OUT ISCP_BERT_REGION_INFO *BertRegionInfo
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);
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/// Register generic hardware error soure
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typedef
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EFI_STATUS
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(EFIAPI *AMD_EXECUTE_REGISTER_ERROR_SOURCE) (
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IN AMD_ISCP_DXE_PROTOCOL *This,
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IN ISCP_TFW_GENERIC_ERROR_SOURCE *GenericErrorSource
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);
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/*----------------------------------------------------------------------------------------
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* P R O T O C O L S T R U C T U R E
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*----------------------------------------------------------------------------------------
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*/
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/// ISCP DXE Protocol Structure
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struct _AMD_ISCP_DXE_PROTOCOL {
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AMD_EXECUTE_CPU_CORE_RESET AmdExecuteCpuCoreReset; ///< Execute CPU Core Reset
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AMD_EXECUTE_CPU_RETRIEVE_ID AmdExecuteCpuRetrieveId; ///< Execute CPU Retrieve ID
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AMD_EXECUTE_GET_MAC_ADDRESS AmdExecuteGetMacAddress; ///< Execute Get MAC Address
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AMD_EXECUTE_SET_MAC_ADDRESS AmdExecuteSetMacAddress; ///< Execute Set MAC Address
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AMD_EXECUTE_GET_RTC AmdExecuteGetRtc; ///< Execute Get Real-Time-Clock Time
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AMD_EXECUTE_SET_RTC AmdExecuteSetRtc; ///< Execute Set Real-Time-Clock Time
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AMD_EXECUTE_UPDATE_FV_BLOCK_DXE AmdExecuteUpdateFvBlockDxe; ///< Execute Update FV Block Data on the SPI device
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AMD_EXECUTE_LOAD_FV_BLOCK_DXE AmdExecuteLoadFvBlockDxe; ///< Execute Load FV Block Data from the SPI device
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AMD_EXECUTE_ERASE_FV_BLOCK_DXE AmdExecuteEraseFvBlockDxe; ///< Execute Erase FV Block Data on the SPI device
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AMD_EXECUTE_UPDATE_EEPROM_BLOCK_DXE AmdExecuteUpdateEepromBlockDxe; ///< Execute Update EEPROM Data on the EEPROM device
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AMD_EXECUTE_LOAD_EEPROM_BLOCK_DXE AmdExecuteLoadEepromBlockDxe; ///< Execute Load EEPROM Data on the EEPROM device
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AMD_EXECUTE_ERASE_EEPROM_BLOCK_DXE AmdExecuteEraseEepromBlockDxe; ///< Execute Erase EEPROM Data on the EEPROM device
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AMD_EXECUTE_GET_BMC_IP_ADDRESS AmdExecuteGetBmcIpAddress; ///< Execute Get BMC IP Address
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AMD_EXECUTE_SMBIOS_INFO AmdExecuteSmbiosInfoDxe; ///< Execute SMBIOS info
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AMD_EXECUTE_SOC_SHUTDOWN AmdExecuteSocShutdownDxe; ///< Execute SoC Shutdown
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AMD_EXECUTE_SOC_RESET AmdExecuteSocResetDxe; ///< Execute SoC Reset
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AMD_EXECUTE_MEM_SETUP AmdExecuteMemSetup; ///< Execute Set MAC Address
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AMD_EXECUTE_OVERRIDE_CMD AmdExecuteOverrideCmd; ///< Execute Override Command
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AMD_EXECUTE_SATA1_GET AmdExecuteSata1Get; ///< Execute Sata1 get state
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AMD_EXECUTE_SATA1_SET AmdExecuteSata1Set; ///< Execute Sata1 set state
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AMD_EXECUTE_BMC_PRESENT AmdExecuteBmcPresent; ///< Execute BMC presence check
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AMD_EXECUTE_RETRIEVE_BERT_RECORD AmdExecuteRetrieveBertRecord; ///< Execute Retrieve Boot Error Record
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AMD_EXECUTE_REGISTER_ERROR_SOURCE AmdExecuteRegisterErrorSource; ///< Execute Register Generic Hardware Error Source
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};
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#endif //_AMD_ISCP_DXE_PROTOCOL_H_
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