/* $NoKeywords */
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/**
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* @file
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*
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* PostCode.h
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*
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* Contains Where's-The-Fimrware (WTF) POST code definitions.
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: FDK
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* @e sub-project: UEFI
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* @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
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*
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*/
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/*****************************************************************************
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*
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* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
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*
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* This program and the accompanying materials are licensed and made available
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* under the terms and conditions of the BSD License which accompanies this
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* distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
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* IMPLIED.
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*
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***************************************************************************/
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#ifndef __POSTCODE__H_
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#define __POSTCODE__H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// AMD UEFI WTF POST Codes
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#define POST_ENTER_SEC_CORE 0x200 ///< Enter SEC Phase Core
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#define POST_INIT_GIG_SEC 0x201 ///< Initialize GIC in Secure Mode
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#define POST_EXIT_SEC_CORE 0x202 ///< Exit SEC Phase Core
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#define POST_INIT_GIC_NON_SEC 0x203 ///< Initalize GIC in Non-Secure Mode
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#define POST_INIT_FV 0x204 ///< Initialize Firmware Volume
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#define POST_RE_INIT_FV 0x205 ///< Re-Initialize Firmware Volume
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#define POST_PROCESS_FV_FILE 0x206 ///< Process Firmware Volume File
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#define POST_PROCESS_FV_FILE_SECT 0x207 ///< Process Firmware Volume Sections
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#define POST_CSP_LIB_INIT_PEI 0x208 ///< Initialize CSP Library PEI Phase
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#define POST_BSP_CORE_MAIN_PRE_PEI 0x209 ///< BSP Core Main Pre-PEI
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#define POST_AP_CORE_MAIN_PRE_PEI 0x20A ///< AP Core Main Pre-PEI
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#define POST_ENTER_PEI_CORE 0x20B ///< Enter PEI Core
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#define POST_INIT_GIC_PEI 0x20C ///< Initialize PEI GIC
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#define POST_UART_INIT 0x20D ///< Initialize UART
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#define POST_UART_INIT_PORT 0x20E ///< Initiaize the UART port attributes
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#define POST_PEI_ISCP_INIT 0x20F ///< Initialize PEI ISCP
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#define POST_EXIT_PEI_CORE 0x210 ///< Exit PEI Core
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#define POST_PRE_PI_MAIN 0x211 ///< Enter Pre-DXE Main
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#define POST_BSP_CORE_MAIN_PRE_PI 0x212 ///< Enter BSP Pre-DXE Core
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#define POST_AP_CORE_MAIN_PRE_PI 0x213 ///< Enter AP Core Main Pre-DXE
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#define POST_DXE_MAIN_UEFI_DECOMP 0x214 ///< Decompress DXE
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#define POST_ENTER_DXE_CORE 0x215 ///< Enter DXE Core
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#define POST_DXE_CORE_MEM_ADD_SPACE 0x216 ///< Add Memory Space in DXE Core
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#define POST_DXE_CORE_MEM_FREE_SPACE 0x217 ///< Free Memory Space in DXE Core
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#define POST_INIT_GIC_DXE 0x218 ///< Initialize GIC in DXE phase
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#define POST_INIT_ISCP_DXE 0x219 ///< Initialize ISCP DXE
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#define POST_EXIT_DXE_CORE 0x21A ///< Exit DXE Core
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#define POST_EXIT_BOOT_SERV 0x21B ///< Exit Boot Services
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#define POST_FINAL 0x3FF ///< Final POST code
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// AMD UEFI WTF Error Codes
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#define ERROR_ISCP_TIMEOUT 0x250 ///< ISCP Timeout (no response from SCP)
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#define ERROR_PXE_DHCP_FAIL 0x251 ///< PXE DHCP Fail
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#define ERROR_PXE_DHCP_PASS 0x252 ///< PXE DHCP Pass
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#define ERROR_PCIE_TRAIN_ERROR 0x261 ///< GIONB PCIE training error
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#define ERROR_PCIE_SPEED_ERROR 0x262 ///< GIONB PCIE data rate error
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#define ERROR_PCIE_PLL_ERROR 0x263 ///< GIONB PCIE PLL error
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#define ERROR_NO_HDD_DETECTED 0x2CF ///< No HDD Detected from SATA ports
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/****** DO NOT WRITE BELOW THIS LINE *******/
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#ifdef __cplusplus
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}
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#endif
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#endif
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