/** @file
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Creates HOB during Standalone MM Foundation entry point
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on ARM platforms.
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Copyright (c) 2017 - 2021, Arm Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiMm.h>
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#include <PiPei.h>
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#include <Guid/MmramMemoryReserve.h>
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#include <Guid/MpInformation.h>
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#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
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#include <Library/ArmMmuLib.h>
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#include <Library/ArmSvcLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/SerialPortLib.h>
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#include <IndustryStandard/ArmStdSmc.h>
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extern EFI_HOB_HANDOFF_INFO_TABLE*
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HobConstructor (
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IN VOID *EfiMemoryBegin,
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IN UINTN EfiMemoryLength,
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IN VOID *EfiFreeMemoryBottom,
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IN VOID *EfiFreeMemoryTop
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);
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// GUID to identify HOB with whereabouts of communication buffer with Normal
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// World
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extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;
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// GUID to identify HOB where the entry point of the CPU driver will be
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// populated to allow this entry point driver to invoke it upon receipt of an
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// event
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extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
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/**
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Use the boot information passed by privileged firmware to populate a HOB list
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suitable for consumption by the MM Core and drivers.
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@param [in, out] CpuDriverEntryPoint Address of MM CPU driver entrypoint
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@param [in] PayloadBootInfo Boot information passed by privileged
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firmware
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**/
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VOID *
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CreateHobListFromBootInfo (
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IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
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IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
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)
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{
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EFI_HOB_HANDOFF_INFO_TABLE *HobStart;
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EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;
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UINT32 Index;
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UINT32 BufferSize;
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UINT32 Flags;
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EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob;
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EFI_MMRAM_DESCRIPTOR *MmramRanges;
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EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;
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MP_INFORMATION_HOB_DATA *MpInformationHobData;
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EFI_PROCESSOR_INFORMATION *ProcInfoBuffer;
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EFI_SECURE_PARTITION_CPU_INFO *CpuInfo;
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ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;
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// Create a hoblist with a PHIT and EOH
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HobStart = HobConstructor (
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(VOID *) (UINTN) PayloadBootInfo->SpMemBase,
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(UINTN) PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase,
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(VOID *) (UINTN) PayloadBootInfo->SpHeapBase,
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(VOID *) (UINTN) (PayloadBootInfo->SpHeapBase + PayloadBootInfo->SpHeapSize)
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);
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// Check that the Hoblist starts at the bottom of the Heap
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ASSERT (HobStart == (VOID *) (UINTN) PayloadBootInfo->SpHeapBase);
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// Build a Boot Firmware Volume HOB
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BuildFvHob (PayloadBootInfo->SpImageBase, PayloadBootInfo->SpImageSize);
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// Build a resource descriptor Hob that describes the available physical
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// memory range
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Attributes = (
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_TESTED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
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);
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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Attributes,
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(UINTN) PayloadBootInfo->SpMemBase,
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PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase
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);
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// Find the size of the GUIDed HOB with MP information
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BufferSize = sizeof (MP_INFORMATION_HOB_DATA);
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BufferSize += sizeof (EFI_PROCESSOR_INFORMATION) * PayloadBootInfo->NumCpus;
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// Create a Guided MP information HOB to enable the ARM TF CPU driver to
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// perform per-cpu allocations.
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MpInformationHobData = BuildGuidHob (&gMpInformationHobGuid, BufferSize);
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// Populate the MP information HOB with the topology information passed by
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// privileged firmware
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MpInformationHobData->NumberOfProcessors = PayloadBootInfo->NumCpus;
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MpInformationHobData->NumberOfEnabledProcessors = PayloadBootInfo->NumCpus;
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ProcInfoBuffer = MpInformationHobData->ProcessorInfoBuffer;
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CpuInfo = PayloadBootInfo->CpuInfo;
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for (Index = 0; Index < PayloadBootInfo->NumCpus; Index++) {
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ProcInfoBuffer[Index].ProcessorId = CpuInfo[Index].Mpidr;
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ProcInfoBuffer[Index].Location.Package = GET_CLUSTER_ID(CpuInfo[Index].Mpidr);
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ProcInfoBuffer[Index].Location.Core = GET_CORE_ID(CpuInfo[Index].Mpidr);
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ProcInfoBuffer[Index].Location.Thread = GET_CORE_ID(CpuInfo[Index].Mpidr);
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Flags = PROCESSOR_ENABLED_BIT | PROCESSOR_HEALTH_STATUS_BIT;
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if (CpuInfo[Index].Flags & CPU_INFO_FLAG_PRIMARY_CPU) {
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Flags |= PROCESSOR_AS_BSP_BIT;
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}
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ProcInfoBuffer[Index].StatusFlag = Flags;
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}
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// Create a Guided HOB to tell the ARM TF CPU driver the location and length
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// of the communication buffer shared with the Normal world.
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NsCommBufMmramRange = (EFI_MMRAM_DESCRIPTOR *) BuildGuidHob (
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&gEfiStandaloneMmNonSecureBufferGuid,
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sizeof (EFI_MMRAM_DESCRIPTOR)
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);
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NsCommBufMmramRange->PhysicalStart = PayloadBootInfo->SpNsCommBufBase;
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NsCommBufMmramRange->CpuStart = PayloadBootInfo->SpNsCommBufBase;
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NsCommBufMmramRange->PhysicalSize = PayloadBootInfo->SpNsCommBufSize;
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NsCommBufMmramRange->RegionState = EFI_CACHEABLE | EFI_ALLOCATED;
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// Create a Guided HOB to enable the ARM TF CPU driver to share its entry
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// point and populate it with the address of the shared buffer
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CpuDriverEntryPointDesc = (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *) BuildGuidHob (
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&gEfiArmTfCpuDriverEpDescriptorGuid,
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sizeof (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR)
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);
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*CpuDriverEntryPoint = NULL;
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CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr = CpuDriverEntryPoint;
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// Find the size of the GUIDed HOB with SRAM ranges
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BufferSize = sizeof (EFI_MMRAM_HOB_DESCRIPTOR_BLOCK);
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BufferSize += PayloadBootInfo->NumSpMemRegions * sizeof (EFI_MMRAM_DESCRIPTOR);
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// Create a GUIDed HOB with SRAM ranges
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MmramRangesHob = BuildGuidHob (&gEfiMmPeiMmramMemoryReserveGuid, BufferSize);
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// Fill up the number of MMRAM memory regions
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MmramRangesHob->NumberOfMmReservedRegions = PayloadBootInfo->NumSpMemRegions;
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// Fill up the MMRAM ranges
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MmramRanges = &MmramRangesHob->Descriptor[0];
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// Base and size of memory occupied by the Standalone MM image
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MmramRanges[0].PhysicalStart = PayloadBootInfo->SpImageBase;
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MmramRanges[0].CpuStart = PayloadBootInfo->SpImageBase;
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MmramRanges[0].PhysicalSize = PayloadBootInfo->SpImageSize;
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MmramRanges[0].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;
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// Base and size of buffer shared with privileged Secure world software
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MmramRanges[1].PhysicalStart = PayloadBootInfo->SpSharedBufBase;
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MmramRanges[1].CpuStart = PayloadBootInfo->SpSharedBufBase;
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MmramRanges[1].PhysicalSize = PayloadBootInfo->SpPcpuSharedBufSize * PayloadBootInfo->NumCpus;
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MmramRanges[1].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;
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// Base and size of buffer used for synchronous communication with Normal
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// world software
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MmramRanges[2].PhysicalStart = PayloadBootInfo->SpNsCommBufBase;
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MmramRanges[2].CpuStart = PayloadBootInfo->SpNsCommBufBase;
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MmramRanges[2].PhysicalSize = PayloadBootInfo->SpNsCommBufSize;
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MmramRanges[2].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;
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// Base and size of memory allocated for stacks for all cpus
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MmramRanges[3].PhysicalStart = PayloadBootInfo->SpStackBase;
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MmramRanges[3].CpuStart = PayloadBootInfo->SpStackBase;
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MmramRanges[3].PhysicalSize = PayloadBootInfo->SpPcpuStackSize * PayloadBootInfo->NumCpus;
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MmramRanges[3].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;
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// Base and size of heap memory shared by all cpus
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MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
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MmramRanges[4].CpuStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
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MmramRanges[4].PhysicalSize = HobStart->EfiFreeMemoryBottom - (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
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MmramRanges[4].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;
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// Base and size of heap memory shared by all cpus
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MmramRanges[5].PhysicalStart = HobStart->EfiFreeMemoryBottom;
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MmramRanges[5].CpuStart = HobStart->EfiFreeMemoryBottom;
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MmramRanges[5].PhysicalSize = HobStart->EfiFreeMemoryTop - HobStart->EfiFreeMemoryBottom;
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MmramRanges[5].RegionState = EFI_CACHEABLE;
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return HobStart;
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}
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