// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* rohm-bu18tl82.c -- I2C register interface access for bu18tl82 serdes chip
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*
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* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
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*
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* Author: luowei <lw@rock-chips.com>
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*/
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#include <serdes-display-core.h>
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#include "rohm-bu18tl82.h"
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#define PINCTRL_GROUP(a, b, c) { .name = a, .pins = b, .num_pins = c}
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static int BU18TL82_GPIO0_pins[] = {0};
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static int BU18TL82_GPIO1_pins[] = {1};
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static int BU18TL82_GPIO2_pins[] = {2};
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static int BU18TL82_GPIO3_pins[] = {3};
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static int BU18TL82_GPIO4_pins[] = {4};
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static int BU18TL82_GPIO5_pins[] = {5};
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static int BU18TL82_GPIO6_pins[] = {6};
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static int BU18TL82_GPIO7_pins[] = {7};
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#define GROUP_DESC(nm) \
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{ \
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.name = #nm, \
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.pins = nm ## _pins, \
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.num_pins = ARRAY_SIZE(nm ## _pins), \
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}
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struct serdes_function_data {
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u8 gpio_rx_en:1;
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u16 gpio_id;
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};
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static const char *serdes_gpio_groups[] = {
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"BU18TL82_GPIO0", "BU18TL82_GPIO1", "BU18TL82_GPIO2", "BU18TL82_GPIO3",
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"BU18TL82_GPIO4", "BU18TL82_GPIO5", "BU18TL82_GPIO6", "BU18TL82_GPIO7",
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};
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/*des -> ser -> soc*/
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#define FUNCTION_DESC_GPIO_INPUT(id) \
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{ \
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.name = "DES_GPIO"#id"_TO_SER", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_rx_en = 0, .gpio_id = (id < 8) ? (id + 2) : (id + 3) } \
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}, \
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} \
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/*soc -> ser -> des*/
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#define FUNCTION_DESC_GPIO_OUTPUT(id) \
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{ \
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.name = "SER_TO_DES_GPIO"#id, \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_rx_en = 1, .gpio_id = (id < 8) ? (id + 2) : (id + 3) } \
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}, \
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} \
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static struct pinctrl_pin_desc bu18tl82_pins_desc[] = {
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PINCTRL_PIN(ROHM_BU18TL82_GPIO0, "BU18TL82_GPIO0"),
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PINCTRL_PIN(ROHM_BU18TL82_GPIO1, "BU18TL82_GPIO1"),
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PINCTRL_PIN(ROHM_BU18TL82_GPIO2, "BU18TL82_GPIO2"),
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PINCTRL_PIN(ROHM_BU18TL82_GPIO3, "BU18TL82_GPIO3"),
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PINCTRL_PIN(ROHM_BU18TL82_GPIO4, "BU18TL82_GPIO4"),
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PINCTRL_PIN(ROHM_BU18TL82_GPIO5, "BU18TL82_GPIO5"),
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PINCTRL_PIN(ROHM_BU18TL82_GPIO6, "BU18TL82_GPIO6"),
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PINCTRL_PIN(ROHM_BU18TL82_GPIO7, "BU18TL82_GPIO7"),
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};
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static struct group_desc bu18tl82_groups_desc[] = {
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GROUP_DESC(BU18TL82_GPIO0),
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GROUP_DESC(BU18TL82_GPIO1),
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GROUP_DESC(BU18TL82_GPIO2),
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GROUP_DESC(BU18TL82_GPIO3),
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GROUP_DESC(BU18TL82_GPIO4),
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GROUP_DESC(BU18TL82_GPIO5),
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GROUP_DESC(BU18TL82_GPIO6),
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GROUP_DESC(BU18TL82_GPIO7),
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};
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static struct function_desc bu18tl82_functions_desc[] = {
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FUNCTION_DESC_GPIO_INPUT(0),
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FUNCTION_DESC_GPIO_INPUT(1),
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FUNCTION_DESC_GPIO_INPUT(2),
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FUNCTION_DESC_GPIO_INPUT(3),
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FUNCTION_DESC_GPIO_INPUT(4),
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FUNCTION_DESC_GPIO_INPUT(5),
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FUNCTION_DESC_GPIO_INPUT(6),
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FUNCTION_DESC_GPIO_INPUT(7),
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FUNCTION_DESC_GPIO_INPUT(8),
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FUNCTION_DESC_GPIO_INPUT(9),
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FUNCTION_DESC_GPIO_INPUT(10),
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FUNCTION_DESC_GPIO_INPUT(11),
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FUNCTION_DESC_GPIO_INPUT(12),
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FUNCTION_DESC_GPIO_INPUT(13),
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FUNCTION_DESC_GPIO_INPUT(14),
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FUNCTION_DESC_GPIO_INPUT(15),
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FUNCTION_DESC_GPIO_OUTPUT(0),
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FUNCTION_DESC_GPIO_OUTPUT(1),
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FUNCTION_DESC_GPIO_OUTPUT(2),
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FUNCTION_DESC_GPIO_OUTPUT(3),
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FUNCTION_DESC_GPIO_OUTPUT(4),
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FUNCTION_DESC_GPIO_OUTPUT(5),
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FUNCTION_DESC_GPIO_OUTPUT(6),
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FUNCTION_DESC_GPIO_OUTPUT(7),
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FUNCTION_DESC_GPIO_OUTPUT(8),
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FUNCTION_DESC_GPIO_OUTPUT(9),
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FUNCTION_DESC_GPIO_OUTPUT(10),
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FUNCTION_DESC_GPIO_OUTPUT(11),
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FUNCTION_DESC_GPIO_OUTPUT(12),
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FUNCTION_DESC_GPIO_OUTPUT(13),
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FUNCTION_DESC_GPIO_OUTPUT(14),
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FUNCTION_DESC_GPIO_OUTPUT(15),
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};
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static struct serdes_chip_pinctrl_info bu18tl82_pinctrl_info = {
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.pins = bu18tl82_pins_desc,
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.num_pins = ARRAY_SIZE(bu18tl82_pins_desc),
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.groups = bu18tl82_groups_desc,
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.num_groups = ARRAY_SIZE(bu18tl82_groups_desc),
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.functions = bu18tl82_functions_desc,
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.num_functions = ARRAY_SIZE(bu18tl82_functions_desc),
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};
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void bu18tl82_bridge_swrst(struct serdes *serdes)
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{
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int ret;
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ret = serdes_reg_write(serdes, BU18TL82_REG_SWRST_INTERNAL, 0x00ef);
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if (ret < 0)
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dev_err(serdes->dev,
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"%s: failed to reset serdes 0x11 ret=%d\n",
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__func__, ret);
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ret = serdes_reg_write(serdes, BU18TL82_REG_SWRST_MIPIRX, 0x0003);
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if (ret < 0)
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dev_err(serdes->dev,
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"%s: failed to reset serdes 0x12 ret=%d\n",
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__func__, ret);
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mdelay(20);
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SERDES_DBG_CHIP("%s: %s ret=%d\n",
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__func__, serdes->dev->name, ret);
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}
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void bu18tl82_enable_hwint(struct serdes *serdes, int enable)
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{
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int i, ret;
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for (i = 0; i < ARRAY_SIZE(bu18tl82_reg_ien); i++) {
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if (enable) {
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ret = serdes_reg_write(serdes, bu18tl82_reg_ien[i].reg,
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bu18tl82_reg_ien[i].ien);
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if (ret)
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printf("%s %s reg 0x%04x write error\n",
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__func__,
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serdes->dev->name, bu18tl82_reg_ien[i].reg);
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} else {
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ret = serdes_reg_write(serdes, bu18tl82_reg_ien[i].reg, 0);
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if (ret)
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printf("%s %s reg 0x%04x write error\n",
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__func__,
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serdes->dev->name, bu18tl82_reg_ien[i].reg);
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}
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}
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SERDES_DBG_CHIP("%s: %s enable=%d\n", __func__,
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serdes->dev->name, enable);
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}
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int bu18tl82_bridge_init(struct serdes *serdes)
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{
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if (!dm_gpio_is_valid(&serdes->reset_gpio))
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bu18tl82_bridge_swrst(serdes);
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SERDES_DBG_CHIP("%s: %s\n", __func__,
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serdes->dev->name);
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return 0;
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}
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int bu18tl82_bridge_enable(struct serdes *serdes)
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{
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return 0;
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}
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int bu18tl82_bridge_disable(struct serdes *serdes)
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{
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return 0;
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}
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int bu18tl82_bridge_get_modes(struct serdes *serdes)
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{
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return 0;
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}
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int bu18tl82_bridge_pre_enable(struct serdes *serdes)
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{
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int ret = 0;
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/* 1:enable 0:dsiable*/
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bu18tl82_enable_hwint(serdes, 0);
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mdelay(160);
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SERDES_DBG_CHIP("%s: %s ret=%d\n", __func__,
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serdes->dev->name, ret);
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return ret;
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}
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bool bu18tl82_bridge_detect(struct serdes *serdes)
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{
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return true;
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}
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static struct serdes_chip_bridge_ops bu18tl82_bridge_ops = {
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.init = bu18tl82_bridge_init,
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.get_modes = bu18tl82_bridge_get_modes,
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.pre_enable = bu18tl82_bridge_pre_enable,
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.enable = bu18tl82_bridge_enable,
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.disable = bu18tl82_bridge_disable,
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.detect = bu18tl82_bridge_detect,
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};
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static int bu18tl82_pinctrl_config_set(struct serdes *serdes,
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unsigned int pin_selector,
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unsigned int param, unsigned int argument)
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{
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switch (param) {
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case PIN_CONFIG_DRIVE_STRENGTH:
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serdes_set_bits(serdes, bu18tl82_gpio_sw[pin_selector].reg,
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bu18tl82_gpio_sw[pin_selector].mask,
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FIELD_PREP(BIT(2) | BIT(1), argument));
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SERDES_DBG_CHIP("%s: serdes %s pin=%d drv arg=0x%x\n",
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__func__,
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serdes->dev->name, pin_selector, argument);
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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serdes_set_bits(serdes, bu18tl82_gpio_pden[pin_selector].reg,
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bu18tl82_gpio_pden[pin_selector].mask,
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FIELD_PREP(BIT(4), argument));
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SERDES_DBG_CHIP("%s: serdes %s pin=%d pull-down arg=0x%x\n",
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__func__,
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serdes->dev->name, pin_selector, argument);
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break;
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case PIN_CONFIG_OUTPUT:
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serdes_set_bits(serdes, bu18tl82_gpio_oen[pin_selector].reg,
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bu18tl82_gpio_oen[pin_selector].mask,
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FIELD_PREP(BIT(3), argument));
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SERDES_DBG_CHIP("%s: serdes %s pin=%d output arg=0x%x\n",
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__func__,
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serdes->dev->name, pin_selector, argument);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int bu18tl82_pinctrl_set_pin_mux(struct serdes *serdes,
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unsigned int pin_selector,
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unsigned int func_selector)
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{
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struct function_desc *func;
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struct pinctrl_pin_desc *pin;
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int offset;
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func = &serdes->chip_data->pinctrl_info->functions[func_selector];
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if (!func) {
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printf("%s: func is null\n", __func__);
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return -EINVAL;
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}
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pin = &serdes->chip_data->pinctrl_info->pins[pin_selector];
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if (!pin) {
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printf("%s: pin is null\n", __func__);
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return -EINVAL;
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}
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SERDES_DBG_CHIP("%s: serdes %s func=%s data=%p pin=%s num=%d\n",
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__func__, serdes->dev->name,
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func->name, func->data,
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pin->name, pin->number);
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if (func->data) {
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struct serdes_function_data *fdata = func->data;
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offset = pin->number;
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if (offset > 7)
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dev_err(serdes->dev, "%s gpio offset=%d > 7\n",
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serdes->dev->name, offset);
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else
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SERDES_DBG_CHIP("%s: serdes %s gpio=0x%x, off=%d\n",
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__func__, serdes->dev->name,
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fdata->gpio_id, offset);
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serdes_set_bits(serdes, bu18tl82_gpio_oen[offset].reg,
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bu18tl82_gpio_oen[offset].mask,
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FIELD_PREP(BIT(3), fdata->gpio_rx_en));
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serdes_set_bits(serdes, bu18tl82_gpio_id_low[offset].reg,
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bu18tl82_gpio_id_low[offset].mask,
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FIELD_PREP(GENMASK(7, 0),
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(fdata->gpio_id & 0xff)));
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serdes_set_bits(serdes, bu18tl82_gpio_id_high[offset].reg,
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bu18tl82_gpio_id_high[offset].mask,
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FIELD_PREP(GENMASK(2, 0),
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((fdata->gpio_id >> 8) & 0x7)));
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serdes_set_bits(serdes, bu18tl82_gpio_pden[offset].reg,
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bu18tl82_gpio_pden[offset].mask,
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FIELD_PREP(BIT(4), 0));
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}
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return 0;
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}
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static int bu18tl82_pinctrl_set_grp_mux(struct serdes *serdes,
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unsigned int group_selector,
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unsigned int func_selector)
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{
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struct serdes_pinctrl *pinctrl = serdes->serdes_pinctrl;
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struct function_desc *func;
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struct group_desc *grp;
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int i, offset;
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func = &serdes->chip_data->pinctrl_info->functions[func_selector];
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if (!func) {
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printf("%s: func is null\n", __func__);
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return -EINVAL;
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}
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grp = &serdes->chip_data->pinctrl_info->groups[group_selector];
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if (!grp) {
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printf("%s: grp is null\n", __func__);
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return -EINVAL;
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}
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SERDES_DBG_CHIP("%s: serdes %s func=%s data=%p grp=%s data=%p, num=%d\n",
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__func__, serdes->dev->name,
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func->name, func->data,
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grp->name, grp->data, grp->num_pins);
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if (func->data) {
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struct serdes_function_data *fdata = func->data;
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for (i = 0; i < grp->num_pins; i++) {
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offset = grp->pins[i] - pinctrl->pin_base;
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if (offset > 7)
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dev_err(serdes->dev, "%s gpio offset=%d > 7\n",
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serdes->dev->name, offset);
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else
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SERDES_DBG_CHIP("%s serdes %s io=0x%x off=%d\n",
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__func__, serdes->dev->name,
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fdata->gpio_id, offset);
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serdes_set_bits(serdes, bu18tl82_gpio_oen[offset].reg,
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bu18tl82_gpio_oen[offset].mask,
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FIELD_PREP(BIT(3), fdata->gpio_rx_en));
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serdes_set_bits(serdes, bu18tl82_gpio_id_low[offset].reg,
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bu18tl82_gpio_id_low[offset].mask,
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FIELD_PREP(GENMASK(7, 0),
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(fdata->gpio_id & 0xff)));
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serdes_set_bits(serdes, bu18tl82_gpio_id_high[offset].reg,
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bu18tl82_gpio_id_high[offset].mask,
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FIELD_PREP(GENMASK(2, 0),
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((fdata->gpio_id >> 8) & 0x7)));
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serdes_set_bits(serdes, bu18tl82_gpio_pden[offset].reg,
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bu18tl82_gpio_pden[offset].mask,
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FIELD_PREP(BIT(4), 0));
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}
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}
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return 0;
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}
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static struct serdes_chip_pinctrl_ops bu18tl82_pinctrl_ops = {
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.pinconf_set = bu18tl82_pinctrl_config_set,
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.pinmux_set = bu18tl82_pinctrl_set_pin_mux,
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.pinmux_group_set = bu18tl82_pinctrl_set_grp_mux,
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};
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static int bu18tl82_gpio_direction_input(struct serdes *serdes, int gpio)
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{
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return 0;
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}
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static int bu18tl82_gpio_direction_output(struct serdes *serdes,
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int gpio, int value)
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{
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return 0;
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}
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static int bu18tl82_gpio_get_level(struct serdes *serdes, int gpio)
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{
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return 0;
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}
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static int bu18tl82_gpio_set_level(struct serdes *serdes,
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int gpio, int value)
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{
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return 0;
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}
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static int bu18tl82_gpio_set_config(struct serdes *serdes,
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int gpio, unsigned long config)
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{
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return 0;
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}
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static int bu18tl82_gpio_to_irq(struct serdes *serdes, int gpio)
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{
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return 0;
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}
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static struct serdes_chip_gpio_ops bu18tl82_gpio_ops = {
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.direction_input = bu18tl82_gpio_direction_input,
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.direction_output = bu18tl82_gpio_direction_output,
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.get_level = bu18tl82_gpio_get_level,
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.set_level = bu18tl82_gpio_set_level,
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.set_config = bu18tl82_gpio_set_config,
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.to_irq = bu18tl82_gpio_to_irq,
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};
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struct serdes_chip_data serdes_bu18tl82_data = {
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.name = "bu18tl82",
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.serdes_type = TYPE_SER,
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.serdes_id = ROHM_ID_BU18TL82,
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.pinctrl_info = &bu18tl82_pinctrl_info,
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.bridge_ops = &bu18tl82_bridge_ops,
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.pinctrl_ops = &bu18tl82_pinctrl_ops,
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.gpio_ops = &bu18tl82_gpio_ops,
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};
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EXPORT_SYMBOL_GPL(serdes_bu18tl82_data);
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MODULE_LICENSE("GPL");
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