/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HALRF_PWR_TABLE_H_
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#define _HALRF_PWR_TABLE_H_
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/*@--------------------------Define Parameters-------------------------------*/
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#define TX_PWR_BY_RATE_NUM_BAND 3
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#define TX_PWR_BY_RATE_NUM_RF 4
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#define PW_LMT_MAX_2G_BANDWITH_NUM 2
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#define PW_LMT_MAX_CHANNEL_NUMBER_2G 14
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#define PW_LMT_MAX_CHANNEL_NUMBER_5G 53
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#define TX_PWR_BY_RATE_NUM_MAC 44
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#define TX_PWR_LIMIT_NUM_MAC 80
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#define TX_PWR_LIMIT_RU_NUM_MAC 30
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#define RADIO_TO_FW_PAGE_SIZE 6
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#define RADIO_TO_FW_DATA_SIZE 500
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/*@-----------------------End Define Parameters-----------------------*/
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/*power by rate*/
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enum halrf_pw_by_rate_para_type {
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PW_BYRATE_PARA_NSS1,
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PW_BYRATE_PARA_NSS2,
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PW_BYRATE_PARA_OFFS = 0xF
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};
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enum halrf_pw_by_rate_rate_type {
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PW_BYRATE_RATE_11M_1M,
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PW_BYRATE_RATE_18M_6M,
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PW_BYRATE_RATE_54M_24M,
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PW_BYRATE_RATE_MCS3_0,
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PW_BYRATE_RATE_MCS7_4,
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PW_BYRATE_RATE_MCS11_8,
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PW_BYRATE_RATE_DCM4_0,
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PW_BYRATE_RATE_AllRate2_1, /* CCK, OFDM, HT, VHT */
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PW_BYRATE_RATE_AllRate2_2, /* HE_HEDCM */
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PW_BYRATE_RATE_AllRate5_1, /* OFDM, HT, VHT, HE_HEDCM */
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PW_BYRATE_RATE_NULL = 0xF
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};
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struct _halrf_file_regd_ext {
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u16 domain;
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char country[2];
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char reg_name[10];
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};
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/*power limit*/
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struct halrf_tx_pw_lmt {
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u8 band;
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u8 bw;
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u8 ntx;
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u8 rs;
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u8 bf;
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u8 reg;
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u8 ch;
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s8 val;
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u8 tx_shap_idx;
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};
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struct halrf_tx_pw_lmt_ru {
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u8 band;
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u8 bw;
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u8 ntx;
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u8 rs;
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u8 reg;
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u8 ch;
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s8 val;
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u8 tx_shap_idx;
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};
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enum halrf_tx_pw_lmt_ru_bandwidth_type {
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PW_LMT_RU_BW_RU26 = 0,
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PW_LMT_RU_BW_RU52,
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PW_LMT_RU_BW_RU106,
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PW_LMT_RU_BW_NULL
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};
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enum halrf_pw_lmt_regulation_type {
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PW_LMT_REGU_WW13 = 0,
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PW_LMT_REGU_ETSI = 1,
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PW_LMT_REGU_FCC = 2,
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PW_LMT_REGU_MKK = 3,
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PW_LMT_REGU_NA = 4,
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PW_LMT_REGU_IC = 5,
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PW_LMT_REGU_KCC = 6,
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PW_LMT_REGU_ACMA = 7,
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PW_LMT_REGU_NCC = 8,
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PW_LMT_REGU_MEXICO = 9,
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PW_LMT_REGU_CHILE = 10,
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PW_LMT_REGU_UKRAINE = 11,
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PW_LMT_REGU_CN = 12,
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PW_LMT_REGU_QATAR = 13,
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/* place predefined ones above */
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PW_LMT_REGU_EXT_PWR,
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PW_LMT_REGU_PREDEF_NUM,
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PW_LMT_REGU_NULL, /* declare this to PW_LMT_MAX_REGULATION_NUM after limit array remove usage of PW_LMT_REGU_NULL */
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PW_LMT_MAX_REGULATION_NUM = 32
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};
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enum halrf_tx_shape_modu_type {
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TX_SHAPE_CCK,
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TX_SHAPE_OFDM,
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TX_SHAPE_MAX
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};
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enum halrf_pw_lmt_band_type {
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PW_LMT_BAND_2_4G = 0,
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PW_LMT_BAND_5G = 1,
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PW_LMT_BAND_6G = 2,
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PW_LMT_MAX_BAND = 3
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};
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enum halrf_pw_lmt_bandwidth_type {
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PW_LMT_BW_20M = 0,
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PW_LMT_BW_40M = 1,
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PW_LMT_BW_80M = 2,
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PW_LMT_BW_160M = 3,
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PW_LMT_MAX_BANDWIDTH_NUM = 4
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};
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enum halrf_pw_lmt_ratesection_type {
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PW_LMT_RS_CCK = 0,
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PW_LMT_RS_OFDM = 1,
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PW_LMT_RS_HT = 2,
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PW_LMT_RS_VHT = 3,
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PW_LMT_RS_HE = 4,
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PW_LMT_MAX_RS_NUM = 5
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};
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enum halrf_pw_lmt_rfpath_type {
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PW_LMT_PH_1T = 0,
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PW_LMT_PH_2T = 1,
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PW_LMT_PH_3T = 2,
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PW_LMT_PH_4T = 3,
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PW_LMT_MAX_PH_NUM = 4
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};
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enum halrf_pw_lmt_beamforming_type {
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PW_LMT_NONBF = 0,
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PW_LMT_BF = 1,
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PW_LMT_MAX_BF_NUM = 2
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};
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enum halrf_data_rate {
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HALRF_DATA_RATE_CCK1 = 0,
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HALRF_DATA_RATE_CCK2 = 0x1,
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HALRF_DATA_RATE_CCK5_5,
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HALRF_DATA_RATE_CCK11,
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HALRF_DATA_RATE_OFDM6,
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HALRF_DATA_RATE_OFDM9,
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HALRF_DATA_RATE_OFDM12,
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HALRF_DATA_RATE_OFDM18,
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HALRF_DATA_RATE_OFDM24,
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HALRF_DATA_RATE_OFDM36,
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HALRF_DATA_RATE_OFDM48 = 10,
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HALRF_DATA_RATE_OFDM54,
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HALRF_DATA_RATE_MCS0,
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HALRF_DATA_RATE_MCS1,
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HALRF_DATA_RATE_MCS2,
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HALRF_DATA_RATE_MCS3,
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HALRF_DATA_RATE_MCS4,
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HALRF_DATA_RATE_MCS5,
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HALRF_DATA_RATE_MCS6,
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HALRF_DATA_RATE_MCS7,
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HALRF_DATA_RATE_MCS8 = 20,
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HALRF_DATA_RATE_MCS9,
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HALRF_DATA_RATE_MCS10,
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HALRF_DATA_RATE_MCS11,
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HALRF_DATA_RATE_MCS12,
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HALRF_DATA_RATE_MCS13,
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HALRF_DATA_RATE_MCS14,
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HALRF_DATA_RATE_MCS15,
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HALRF_DATA_RATE_MCS16,
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HALRF_DATA_RATE_MCS17,
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HALRF_DATA_RATE_MCS18 = 30,
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HALRF_DATA_RATE_MCS19,
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HALRF_DATA_RATE_MCS20,
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HALRF_DATA_RATE_MCS21,
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HALRF_DATA_RATE_MCS22,
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HALRF_DATA_RATE_MCS23,
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HALRF_DATA_RATE_MCS24,
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HALRF_DATA_RATE_MCS25,
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HALRF_DATA_RATE_MCS26,
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HALRF_DATA_RATE_MCS27,
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HALRF_DATA_RATE_MCS28 = 40,
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HALRF_DATA_RATE_MCS29,
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HALRF_DATA_RATE_MCS30,
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HALRF_DATA_RATE_MCS31,
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HALRF_DATA_RATE_VHT_NSS1_MCS0,
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HALRF_DATA_RATE_VHT_NSS1_MCS1,
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HALRF_DATA_RATE_VHT_NSS1_MCS2,
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HALRF_DATA_RATE_VHT_NSS1_MCS3,
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HALRF_DATA_RATE_VHT_NSS1_MCS4,
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HALRF_DATA_RATE_VHT_NSS1_MCS5,
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HALRF_DATA_RATE_VHT_NSS1_MCS6 = 50,
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HALRF_DATA_RATE_VHT_NSS1_MCS7,
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HALRF_DATA_RATE_VHT_NSS1_MCS8,
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HALRF_DATA_RATE_VHT_NSS1_MCS9,
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HALRF_DATA_RATE_VHT_NSS2_MCS0,
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HALRF_DATA_RATE_VHT_NSS2_MCS1,
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HALRF_DATA_RATE_VHT_NSS2_MCS2,
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HALRF_DATA_RATE_VHT_NSS2_MCS3,
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HALRF_DATA_RATE_VHT_NSS2_MCS4,
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HALRF_DATA_RATE_VHT_NSS2_MCS5,
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HALRF_DATA_RATE_VHT_NSS2_MCS6 = 60,
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HALRF_DATA_RATE_VHT_NSS2_MCS7,
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HALRF_DATA_RATE_VHT_NSS2_MCS8,
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HALRF_DATA_RATE_VHT_NSS2_MCS9,
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HALRF_DATA_RATE_VHT_NSS3_MCS0,
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HALRF_DATA_RATE_VHT_NSS3_MCS1,
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HALRF_DATA_RATE_VHT_NSS3_MCS2,
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HALRF_DATA_RATE_VHT_NSS3_MCS3,
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HALRF_DATA_RATE_VHT_NSS3_MCS4,
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HALRF_DATA_RATE_VHT_NSS3_MCS5,
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HALRF_DATA_RATE_VHT_NSS3_MCS6 = 70,
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HALRF_DATA_RATE_VHT_NSS3_MCS7,
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HALRF_DATA_RATE_VHT_NSS3_MCS8,
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HALRF_DATA_RATE_VHT_NSS3_MCS9,
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HALRF_DATA_RATE_VHT_NSS4_MCS0,
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HALRF_DATA_RATE_VHT_NSS4_MCS1,
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HALRF_DATA_RATE_VHT_NSS4_MCS2,
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HALRF_DATA_RATE_VHT_NSS4_MCS3,
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HALRF_DATA_RATE_VHT_NSS4_MCS4,
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HALRF_DATA_RATE_VHT_NSS4_MCS5,
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HALRF_DATA_RATE_VHT_NSS4_MCS6 = 80,
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HALRF_DATA_RATE_VHT_NSS4_MCS7,
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HALRF_DATA_RATE_VHT_NSS4_MCS8,
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HALRF_DATA_RATE_VHT_NSS4_MCS9,
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HALRF_DATA_RATE_HE_NSS1_MCS0,
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HALRF_DATA_RATE_HE_NSS1_MCS1,
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HALRF_DATA_RATE_HE_NSS1_MCS2,
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HALRF_DATA_RATE_HE_NSS1_MCS3,
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HALRF_DATA_RATE_HE_NSS1_MCS4,
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HALRF_DATA_RATE_HE_NSS1_MCS5,
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HALRF_DATA_RATE_HE_NSS1_MCS6 = 90,
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HALRF_DATA_RATE_HE_NSS1_MCS7,
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HALRF_DATA_RATE_HE_NSS1_MCS8,
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HALRF_DATA_RATE_HE_NSS1_MCS9,
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HALRF_DATA_RATE_HE_NSS1_MCS10,
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HALRF_DATA_RATE_HE_NSS1_MCS11,
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HALRF_DATA_RATE_HE_NSS2_MCS0,
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HALRF_DATA_RATE_HE_NSS2_MCS1,
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HALRF_DATA_RATE_HE_NSS2_MCS2,
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HALRF_DATA_RATE_HE_NSS2_MCS3,
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HALRF_DATA_RATE_HE_NSS2_MCS4 = 100,
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HALRF_DATA_RATE_HE_NSS2_MCS5,
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HALRF_DATA_RATE_HE_NSS2_MCS6,
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HALRF_DATA_RATE_HE_NSS2_MCS7,
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HALRF_DATA_RATE_HE_NSS2_MCS8,
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HALRF_DATA_RATE_HE_NSS2_MCS9,
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HALRF_DATA_RATE_HE_NSS2_MCS10,
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HALRF_DATA_RATE_HE_NSS2_MCS11,
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HALRF_DATA_RATE_HE_NSS3_MCS0,
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HALRF_DATA_RATE_HE_NSS3_MCS1,
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HALRF_DATA_RATE_HE_NSS3_MCS2 = 110,
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HALRF_DATA_RATE_HE_NSS3_MCS3,
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HALRF_DATA_RATE_HE_NSS3_MCS4,
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HALRF_DATA_RATE_HE_NSS3_MCS5,
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HALRF_DATA_RATE_HE_NSS3_MCS6,
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HALRF_DATA_RATE_HE_NSS3_MCS7,
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HALRF_DATA_RATE_HE_NSS3_MCS8,
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HALRF_DATA_RATE_HE_NSS3_MCS9,
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HALRF_DATA_RATE_HE_NSS3_MCS10,
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HALRF_DATA_RATE_HE_NSS3_MCS11,
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HALRF_DATA_RATE_HE_NSS4_MCS0 = 120,
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HALRF_DATA_RATE_HE_NSS4_MCS1,
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HALRF_DATA_RATE_HE_NSS4_MCS2,
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HALRF_DATA_RATE_HE_NSS4_MCS3,
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HALRF_DATA_RATE_HE_NSS4_MCS4,
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HALRF_DATA_RATE_HE_NSS4_MCS5,
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HALRF_DATA_RATE_HE_NSS4_MCS6,
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HALRF_DATA_RATE_HE_NSS4_MCS7,
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HALRF_DATA_RATE_HE_NSS4_MCS8,
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HALRF_DATA_RATE_HE_NSS4_MCS9,
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HALRF_DATA_RATE_HE_NSS4_MCS10 = 130,
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HALRF_DATA_RATE_HE_NSS4_MCS11,
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HALRF_DATA_RATE_HEDCM_NSS1_MCS0,
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HALRF_DATA_RATE_HEDCM_NSS1_MCS1,
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HALRF_DATA_RATE_HEDCM_NSS1_MCS3,
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HALRF_DATA_RATE_HEDCM_NSS1_MCS4,
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HALRF_DATA_RATE_HEDCM_NSS2_MCS0,
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HALRF_DATA_RATE_HEDCM_NSS2_MCS1,
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HALRF_DATA_RATE_HEDCM_NSS2_MCS3,
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HALRF_DATA_RATE_HEDCM_NSS2_MCS4,
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HALRF_DATA_RATE_HEDCM_OFFSET = 140,
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HALRF_DATA_RATE_VHT_OFFSET,
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HALRF_DATA_RATE_HT_OFFSET,
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HALRF_DATA_RATE_OFDM_OFFSET,
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HALRF_DATA_RATE_CCK_OFFSET,
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HALRF_DATA_RATE_MAX
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};
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struct halrf_pwr_info {
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/*Power by Rate and Power Limit Switch*/
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u8 pwr_table_switch_efuse;
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u8 pwr_by_rate_switch;
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u8 pwr_limit_switch;
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bool regulation[PW_LMT_MAX_BAND][PW_LMT_MAX_REGULATION_NUM];
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u8 tx_shap_idx[PW_LMT_MAX_BAND][TX_SHAPE_MAX][PW_LMT_MAX_REGULATION_NUM];
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s8 tx_pwr_by_rate[TX_PWR_BY_RATE_NUM_BAND][HALRF_DATA_RATE_MAX];
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s8 tx_pwr_limit_2g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_MAX_2G_BANDWITH_NUM]
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[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_2G][MAX_HALRF_PATH];
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s8 tx_pwr_limit_5g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_MAX_BANDWIDTH_NUM]
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[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_5G][MAX_HALRF_PATH];
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s8 tx_pwr_limit_ru_2g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_RU_BW_NULL]
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[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_2G][MAX_HALRF_PATH];
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s8 tx_pwr_limit_ru_5g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_RU_BW_NULL]
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[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_5G][MAX_HALRF_PATH];
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s8 tx_pwr_by_rate_mac[HW_PHY_MAX][TX_PWR_BY_RATE_NUM_MAC];
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s8 tx_pwr_limit_mac[HW_PHY_MAX][TX_PWR_LIMIT_NUM_MAC];
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s8 tx_pwr_limit_ru_mac[HW_PHY_MAX][TX_PWR_LIMIT_RU_NUM_MAC];
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s16 tx_pwr_limit_ru26_mac[HW_PHY_MAX];
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s16 tx_pwr_limit_ru52_mac[HW_PHY_MAX];
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s16 tx_pwr_limit_ru106_mac[HW_PHY_MAX];
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bool coex_pwr_ctl_enable;
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bool dpk_pwr_ctl_enable;
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s32 coex_pwr;
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s32 dpk_pwr;
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u8 mp_regulation;
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u8 regulation_idx;
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u8 regulation_str[10];
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bool fix_power[MAX_HALRF_PATH];
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s8 fix_power_dbm[MAX_HALRF_PATH];
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bool set_tx_ptrn_shap_en;
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u8 set_tx_ptrn_shap_idx[PW_LMT_MAX_BAND][TX_SHAPE_MAX];
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};
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extern const char * const _pw_lmt_regu_type_str[PW_LMT_MAX_REGULATION_NUM];
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#define pw_lmt_regu_type_str(lmt) ((lmt) < PW_LMT_MAX_REGULATION_NUM ? _pw_lmt_regu_type_str[(lmt)] : NULL)
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extern const enum halrf_pw_lmt_regulation_type _regulation_to_pw_lmt_regu_type[REGULATION_MAX];
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#define regulation_to_pw_lmt_regu_type(reg) ((reg) < REGULATION_MAX ? _regulation_to_pw_lmt_regu_type[(reg)] : PW_LMT_REGU_WW13)
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extern const enum halrf_pw_lmt_regulation_type _tpo_to_pw_lmt_regu_type[TPO_NA];
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#define tpo_to_pw_lmt_regu_type(reg) ((reg) < TPO_NA ? _tpo_to_pw_lmt_regu_type[(reg)] : PW_LMT_REGU_WW13)
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u8 halrf_get_regulation_info(struct rf_info *rf, u8 band);
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void halrf_power_by_rate_store_to_array(struct rf_info *rf,
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u32 band, u32 tx_num, u32 rate_id, u32 data);
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void halrf_power_limit_store_to_array(struct rf_info *rf,
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u8 regulation, u8 band, u8 bandwidth, u8 rate,
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u8 tx_num, u8 beamforming, u8 chnl, s8 val);
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void halrf_power_limit_set_worldwide(struct rf_info *rf);
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void halrf_power_limit_ru_store_to_array(struct rf_info *rf,
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u8 band, u8 bandwidth, u8 tx_num, u8 rate,
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u8 regulation, u8 chnl, s8 val);
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void halrf_power_limit_ru_set_worldwide(struct rf_info *rf);
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u8 halrf_get_power_limit_extra(struct rf_info *rf);
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#endif
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