/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HALRF_PMAC_H_
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#define _HALRF_PMAC_H_
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/*@--------------------------[Define] ---------------------------------------*/
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/*@--------------------------[Enum]------------------------------------------*/
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enum rf_ppdu_type {
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T_CCK = 0,
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T_LEGACY = 1,
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T_HT_MF = 2,
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T_VHT = 3,
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T_HE_SU = 4,
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T_HE_ER_SU = 5,
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T_HE_MU_OFDMA = 6,
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T_HE_TB = 7,
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct rf_pmac_tx_info {
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enum rf_ppdu_type ppdu;
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u8 mcs;
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u8 bw;
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u8 nss;
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u8 long_preamble_en;
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u8 gi;
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u16 case_id;
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s16 dbm;
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u16 txagc_cw;
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u8 is_cck;
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u16 cnt;
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u16 time;
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u16 period;
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u16 length;
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};
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struct rf_usr_plcp_gen_in {
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u32 mcs : 6;
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u32 mpdu_len : 14;
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u32 n_mpdu : 9;
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u32 fec : 1;
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u32 dcm : 1;
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u32 rsvd0 : 1;
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u32 aid : 12;
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u32 scrambler_seed : 8; // rand (1~255)
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u32 random_init_seed : 8; // rand (1~255)
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u32 rsvd1 : 4;
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u32 apep : 22;
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u32 ru_alloc : 8;
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u32 rsvd2 : 2;
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u32 nss : 4;
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u32 txbf : 1;
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u32 pwr_boost_db : 5;
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u32 rsvd3 : 22;
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};
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struct rf_plcp_param_t {
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u32 dbw : 2; //0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80
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u32 source_gen_mode : 2;
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u32 locked_clk : 1;
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u32 dyn_bw : 1;
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u32 ndp_en : 1;
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u32 long_preamble_en : 1; //bmode
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u32 stbc : 1;
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u32 gi : 2; //0:0.4,1:0.8,2:1.6,3:3.2
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u32 tb_l_len : 12;
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u32 tb_ru_tot_sts_max : 3;
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u32 vht_txop_not_allowed : 1;
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u32 tb_disam : 1;
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u32 doppler : 2;
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u32 he_ltf_type : 2;//0:1x,1:2x,2:4x
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u32 ht_l_len : 12;
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u32 preamble_puncture : 1;
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u32 he_mcs_sigb : 3;//0~5
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u32 he_dcm_sigb : 1;
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u32 he_sigb_compress_en : 1;
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u32 max_tx_time_0p4us : 14;
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u32 ul_flag : 1;
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u32 tb_ldpc_extra : 1;
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u32 bss_color : 6;
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u32 sr : 4;
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u32 beamchange_en : 1;
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u32 he_er_u106ru_en : 1;
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u32 ul_srp1 : 4;
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u32 ul_srp2 : 4;
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u32 ul_srp3 : 4;
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u32 ul_srp4 : 4;
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u32 mode : 2;
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u32 group_id : 6;
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u32 ppdu_type : 4;//0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB
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u32 txop : 7;
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u32 tb_strt_sts : 3;
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u32 tb_pre_fec_padding_factor : 2;
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u32 cbw : 2;
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u32 txsc : 4;
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u32 tb_mumimo_mode_en : 1;
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u32 rsvd1 : 3;
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u8 nominal_t_pe : 2; // def = 2
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u8 ness : 2; // def = 0
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u8 rsvd2 : 4;
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u8 n_user;
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u16 tb_rsvd : 9;//def = 0
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u16 rsvd3 : 7;
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struct rf_usr_plcp_gen_in usr[4];
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};
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/*@--------------------------[Prptotype]-------------------------------------*/
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void halrf_set_pmac_cw(struct rf_info *rf, enum rf_path path, u16 txagc_cw, bool en);
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void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx,
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enum rf_path path, struct rf_pmac_tx_info *tx,
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u8 enable, bool by_cw);
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void halrf_set_pseudo_cw(struct rf_info *rf, enum rf_path path,
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u16 txagc_cw, bool en);
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#if 0
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void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx,
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enum rf_path path, u8 ppdu_type, u8 case_id, s16 dbm,
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u8 enable, u8 is_cck, u16 cnt ,u16 time, u16 period);
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#endif
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#endif
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