/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "halrf_precomp.h"
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u32 halrf_get_sys_time(struct rf_info *rf)
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{
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return 0;
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}
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u32 halrf_cal_bit_shift(u32 bit_mask)
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{
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u32 i;
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for (i = 0; i <= 31; i++) {
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if ((bit_mask >> i) & BIT0)
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break;
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}
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return i;
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}
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void halrf_wreg(struct rf_info *rf, u32 addr, u32 mask, u32 val)
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{
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u32 ori_val, bit_shift;
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#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
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struct rtw_mac_cmd cmd = {0};
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struct halrf_fw_offload *fwofld_info = &rf->fwofld;
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u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
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u32 rtn;
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#endif
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// u32 page_temp;
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// u32 offset_temp;
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// u32 temp = 0;
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// page_temp = addr & 0xff00;
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// offset_temp = addr & 0xff;
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// if ((page_temp != 0x4c00) && (page_temp != 0x4d00)) {
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// if (offset_temp <= 0x9c)
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// temp = halrf_r32(rf, offset_temp | 0x4c00);
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// }
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#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
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if (fw_ofld == true && rf->fw_ofld_enable == true) {
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RF_DBG(rf, DBG_RF_FW,
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"[FW_Ofld] addr=0x%08x mask=0x%08x val=0x%08x\n",
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addr, mask, val);
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hal_mem_set(rf->hal_com, fwofld_info, 0, sizeof(*fwofld_info));
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cmd.src = RTW_MAC_BB_CMD_OFLD;
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cmd.type = RTW_MAC_WRITE_OFLD;
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cmd.lc = 0;
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cmd.offset = (u16)addr;
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cmd.value = val;
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cmd.mask = mask;
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fwofld_info->src = RTW_MAC_BB_CMD_OFLD;
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fwofld_info->type = RTW_MAC_WRITE_OFLD;
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fwofld_info->lc = 1;
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fwofld_info->offset = (u16)addr;
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fwofld_info->value = val;
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fwofld_info->mask = mask;
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rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
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if (rtn) {
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RF_WARNING("======>%s return fail error code = %d !!!\n",
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__func__, rtn);
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}
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}
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else
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#endif
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{
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if (mask != MASKDWORD) {
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ori_val = halrf_r32(rf, addr);
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bit_shift = halrf_cal_bit_shift(mask);
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val = ((ori_val) & (~mask)) |( ((val << bit_shift)) & mask);
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}
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halrf_w32(rf, addr, val);
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}
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// if ((page_temp != 0x4c00) && (page_temp != 0x4d00)) {
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// if (offset_temp <= 0x9c)
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// halrf_w32(rf, offset_temp | 0x4c00, temp);
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// }
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}
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u32 halrf_rreg(struct rf_info *rf, u32 addr, u32 mask)
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{
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u32 reg_val = 0, ori_val, bit_shift;
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ori_val = halrf_r32(rf, addr);
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bit_shift = halrf_cal_bit_shift(mask);
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reg_val = (ori_val & mask) >> bit_shift;
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return reg_val;
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}
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void halrf_wrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask, u32 val)
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{
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#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
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struct rtw_mac_cmd cmd = {0};
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struct halrf_fw_offload *fwofld_info = &rf->fwofld;
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u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
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u32 rtn;
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if (fw_ofld == true && rf->fw_ofld_enable == true) {
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RF_DBG(rf, DBG_RF_FW,
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"[FW_Ofld] addr=0x%08x mask=0x%08x val=0x%08x path=%d\n",
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addr, mask, val, path);
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hal_mem_set(rf->hal_com, fwofld_info, 0, sizeof(*fwofld_info));
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cmd.src = RTW_MAC_RF_CMD_OFLD;
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cmd.type = RTW_MAC_WRITE_OFLD;
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cmd.lc = 0;
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cmd.rf_path = path;
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cmd.offset = (u16)addr;
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cmd.value = val;
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cmd.mask = mask;
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fwofld_info->src = RTW_MAC_RF_CMD_OFLD;
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fwofld_info->type = RTW_MAC_WRITE_OFLD;
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fwofld_info->lc = 1;
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fwofld_info->rf_path = path;
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fwofld_info->offset = (u16)addr;
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fwofld_info->value = val;
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fwofld_info->mask = mask;
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rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
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if (rtn) {
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RF_WARNING("======>%s return fail error code = %d !!!\n",
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__func__, rtn);
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}
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} else
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#endif
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rtw_hal_write_rf_reg((rf)->hal_com, path, addr, mask, val);
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}
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void halrf_delay_10us(struct rf_info *rf, u32 count)
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{
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u32 i;
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for (i = 0; i < count; i++)
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halrf_delay_us(rf, 10);
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}
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void halrf_fill_h2c_cmd(struct rf_info *rf, u16 cmdlen, u8 cmdid,
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u8 classid, u32 cmdtype, u32 *pval)
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{
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u32 rt_val = 0;
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struct rtw_g6_h2c_hdr hdr = {0};
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struct rtw_hal_com_t *hal_com = NULL;
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hdr.h2c_class = classid;
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hdr.h2c_func = cmdid;
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hdr.type = cmdtype;
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hdr.content_len = cmdlen;
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hal_com = rf->hal_com;
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RF_DBG(rf, DBG_RF_IQK, "[IQK]======>%s H2C: %x %x %x\n",
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__func__, classid, cmdid, cmdlen);
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rt_val = rtw_hal_mac_send_h2c(hal_com, &hdr, pval);
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if (rt_val != 0) {
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RF_WARNING("Error H2C CLASS=%d, ID=%d\n", classid, cmdid);
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RF_DBG(rf, DBG_RF_IQK, "Error H2C CLASS=%d, ID=%d\n", classid, cmdid);
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}
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}
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