/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#include "../halrf_precomp.h"
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#ifdef RF_8852B_SUPPORT
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void _halrf_psd_backup_bb_registers_8852b(
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struct rf_info *rf,
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enum phl_phy_idx phy,
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u32 *reg,
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u32 *reg_backup,
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u32 reg_num)
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{
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u32 i;
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for (i = 0; i < reg_num; i++) {
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reg_backup[i] = halrf_rreg(rf, reg[i], MASKDWORD);
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RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Backup BB 0x%08x = 0x%08x\n",
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reg[i], reg_backup[i]);
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}
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}
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void _halrf_psd_reload_bb_registers_8852b(
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struct rf_info *rf,
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enum phl_phy_idx phy,
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u32 *reg,
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u32 *reg_backup,
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u32 reg_num)
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{
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u32 i;
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for (i = 0; i < reg_num; i++) {
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halrf_wreg(rf, reg[i], MASKDWORD, reg_backup[i]);
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RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Reload BB 0x%08x = 0x%08x\n",
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reg[i], reg_backup[i]);
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}
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}
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void halrf_psd_init_8852b(struct rf_info *rf, enum phl_phy_idx phy,
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u8 path, u8 iq_path, u32 avg, u32 fft)
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{
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struct halrf_psd_data *psd_info = &rf->psd;
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u32 bb_reg[PSD_BACKUP_NUM_8852B] = {
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0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8,
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0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008,
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0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c,
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0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490,
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0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088,
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0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120,
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0x8220, 0x8018, 0x8000, 0x800c, 0x81cc,
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0x82cc, 0x802c, 0x8034, 0x80d4, 0x80fc,
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0x801c};
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RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d\n", __func__, phy);
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psd_info->psd_progress = 1;
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_halrf_psd_backup_bb_registers_8852b(rf, phy, bb_reg,
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psd_info->psd_reg_backup, PSD_BACKUP_NUM_8852B);
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psd_info->path = path;
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psd_info->iq_path = iq_path;
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psd_info->avg = avg;
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psd_info->fft = fft;
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/*02_BB_AFE_PHY0*/
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halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0303);
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halrf_wreg(rf, 0x5864, 0x18000000, 0x3);
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halrf_wreg(rf, 0x7864, 0x18000000, 0x3);
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halrf_wreg(rf, 0x12b8, 0x40000000, 0x1);
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halrf_wreg(rf, 0x32b8, 0x40000000, 0x1);
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halrf_wreg(rf, 0x030c, 0xff000000, 0x13);
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halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041);
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halrf_wreg(rf, 0x12b8, 0x10000000, 0x1);
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halrf_wreg(rf, 0x58c8, 0x01000000, 0x1);
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halrf_wreg(rf, 0x78c8, 0x01000000, 0x1);
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halrf_wreg(rf, 0x5864, 0xc0000000, 0x3);
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halrf_wreg(rf, 0x7864, 0xc0000000, 0x3);
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halrf_wreg(rf, 0x2008, 0x01ffffff, 0x1ffffff);
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halrf_wreg(rf, 0x0c1c, 0x00000004, 0x1);
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halrf_wreg(rf, 0x0700, 0x08000000, 0x1);
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halrf_wreg(rf, 0x0c70, 0x000003ff, 0x3ff);
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halrf_wreg(rf, 0x0c60, 0x00000003, 0x3);
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halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1);
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halrf_wreg(rf, 0x58ac, 0x08000000, 0x1);
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halrf_wreg(rf, 0x78ac, 0x08000000, 0x1);
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halrf_wreg(rf, 0x0c3c, 0x00000200, 0x1);
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halrf_wreg(rf, 0x2320, 0x00000001, 0x1);
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halrf_wreg(rf, 0x4490, 0x80000000, 0x1);
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halrf_wreg(rf, 0x12a0, 0x00007000, 0x7);
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halrf_wreg(rf, 0x12a0, 0x00008000, 0x1);
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halrf_wreg(rf, 0x12a0, 0x00070000, 0x3);
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halrf_wreg(rf, 0x12a0, 0x00080000, 0x1);
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halrf_wreg(rf, 0x32a0, 0x00070000, 0x3);
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halrf_wreg(rf, 0x32a0, 0x00080000, 0x1);
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halrf_wreg(rf, 0x0700, 0x01000000, 0x1);
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halrf_wreg(rf, 0x0700, 0x06000000, 0x2);
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halrf_wreg(rf, 0x20fc, 0xffff0000, 0x3333);
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/*03_IQK_Preset_Non_DBCC_PHY0*/
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halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x0);
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halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x0);
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halrf_wreg(rf, 0x8008, 0xffffffff, 0x00000080);
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halrf_wreg(rf, 0x8080, 0xffffffff, 0x00000000);
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halrf_wreg(rf, 0x8088, 0xffffffff, 0x81ff010a);
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halrf_wreg(rf, 0x80d0, 0xffffffff, 0x00200000);
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halrf_wreg(rf, 0x8074, 0xffffffff, 0x80000000);
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halrf_wreg(rf, 0x81dc, 0xffffffff, 0x00000000);
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halrf_wreg(rf, 0x82dc, 0xffffffff, 0x00000000);
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/*07_CLK_Setting_RxIQK_BW80M_Non_DBCC_PHY0*/
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halrf_wreg(rf, 0x8120, 0xffffffff, 0x4d000a08);
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halrf_wreg(rf, 0x8220, 0xffffffff, 0x4d000a08);
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halrf_wreg(rf, 0x12a0, 0x00070000, 0x2);
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halrf_wreg(rf, 0x12a0, 0x00080000, 0x1);
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halrf_wreg(rf, 0x32a0, 0x00070000, 0x2);
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halrf_wreg(rf, 0x32a0, 0x00080000, 0x1);
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halrf_wreg(rf, 0x0700, 0x01000000, 0x1);
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halrf_wreg(rf, 0x0700, 0x06000000, 0x1);
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/*windowing*/
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halrf_wreg(rf, 0x8018, 0xfffffffe, 0x20008080);
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if (fft == 160)
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halrf_wreg(rf, 0x801c, 0x00003000, 0x0);
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else if (fft == 320)
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halrf_wreg(rf, 0x801c, 0x00003000, 0x1);
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else if (fft == 640)
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halrf_wreg(rf, 0x801c, 0x00003000, 0x2);
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else /*1280*/
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halrf_wreg(rf, 0x801c, 0x00003000, 0x3);
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if (avg == 1)
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halrf_wreg(rf, 0x801c, 0x000e0000, 0x0);
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else if (avg == 2)
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halrf_wreg(rf, 0x801c, 0x000e0000, 0x1);
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else if (avg == 4)
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halrf_wreg(rf, 0x801c, 0x000e0000, 0x2);
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else if (avg == 8)
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halrf_wreg(rf, 0x801c, 0x000e0000, 0x3);
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else if (avg == 16)
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halrf_wreg(rf, 0x801c, 0x000e0000, 0x4);
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else if (avg == 64)
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halrf_wreg(rf, 0x801c, 0x000e0000, 0x6);
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else if (avg == 128)
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halrf_wreg(rf, 0x801c, 0x000e0000, 0x7);
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else /*32*/
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halrf_wreg(rf, 0x801c, 0x000e0000, 0x5);
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}
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void halrf_psd_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy)
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{
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struct halrf_psd_data *psd_info = &rf->psd;
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u32 bb_reg[PSD_BACKUP_NUM_8852B] = {
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0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8,
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0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008,
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0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c,
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0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490,
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0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088,
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0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120,
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0x8220, 0x8018, 0x8000, 0x800c, 0x81cc,
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0x82cc, 0x802c, 0x8034, 0x80d4, 0x80fc,
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0x801c};
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RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d\n", __func__, phy);
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_halrf_psd_reload_bb_registers_8852b(rf, phy, bb_reg,
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psd_info->psd_reg_backup, PSD_BACKUP_NUM_8852B);
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halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x1);
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halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x1);
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psd_info->psd_progress = 0;
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#if 0
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/*98_IQK_Reg_Non_DBCC_PHY0_path01_Restore*/
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halrf_wreg(rf, 0x8008, 0xffffffff, 0x00000000);
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halrf_wreg(rf, 0x8074, 0xffffffff, 0x00000000);
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halrf_wreg(rf, 0x8088, 0xffffffff, 0x80000000);
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halrf_wreg(rf, 0x80d0, 0xffffffff, 0x00000000);
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halrf_wreg(rf, 0x80e0, 0x00000001, 0x0);
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halrf_wreg(rf, 0x8120, 0xffffffff, 0x10010000);
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halrf_wreg(rf, 0x8140, 0x00000100, 0x0);
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halrf_wreg(rf, 0x8150, 0xffffffff, 0xe4e4e4e4);
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halrf_wreg(rf, 0x8154, 0x00000100, 0x0);
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halrf_wreg(rf, 0x81cc, 0x0000003f, 0x0);
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halrf_wreg(rf, 0x81dc, 0xffffffff, 0x00000002);
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halrf_wreg(rf, 0x8220, 0xffffffff, 0x10010000);
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halrf_wreg(rf, 0x8240, 0x00000100, 0x0);
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halrf_wreg(rf, 0x8250, 0xffffffff, 0xe4e4e4e4);
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halrf_wreg(rf, 0x8254, 0x00000100, 0x0);
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halrf_wreg(rf, 0x82cc, 0x0000003f, 0x0);
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halrf_wreg(rf, 0x82dc, 0xffffffff, 0x00000002);
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/*99_BB_AFE_Non_DBCC_PHY0_path01_restore*/
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halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0303);
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halrf_wreg(rf, 0x12b8, 0x40000000, 0x0);
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halrf_wreg(rf, 0x32b8, 0x40000000, 0x0);
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halrf_wreg(rf, 0x5864, 0xc0000000, 0x0);
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halrf_wreg(rf, 0x7864, 0xc0000000, 0x0);
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halrf_wreg(rf, 0x2008, 0x01ffffff, 0x0000000);
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halrf_wreg(rf, 0x0c1c, 0x00000004, 0x0);
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halrf_wreg(rf, 0x0700, 0x08000000, 0x0);
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halrf_wreg(rf, 0x0c70, 0x0000001f, 0x03);
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halrf_wreg(rf, 0x0c70, 0x000003e0, 0x03);
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halrf_wreg(rf, 0x12a0, 0x000ff000, 0x00);
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halrf_wreg(rf, 0x32a0, 0x000ff000, 0x00);
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halrf_wreg(rf, 0x0700, 0x07000000, 0x0);
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halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0);
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halrf_wreg(rf, 0x2320, 0x00000001, 0x0);
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halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000);
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halrf_wreg(rf, 0x58c8, 0x01000000, 0x0);
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halrf_wreg(rf, 0x78c8, 0x01000000, 0x0);
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#endif
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}
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u32 halrf_psd_get_point_data_8852b(struct rf_info *rf,
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enum phl_phy_idx phy, s32 point)
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{
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struct halrf_psd_data *psd_info = &rf->psd;
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u32 val_tmp, val, data;
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halrf_wreg(rf, 0x8088, 0xffffffff, 0x81ff0109);
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if (psd_info->path == RF_PATH_A)
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halrf_wreg(rf, 0x8000, 0xffffffff, 0x00000008);
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else
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halrf_wreg(rf, 0x8000, 0xffffffff, 0x0000000a);
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halrf_wreg(rf, 0x800c, 0xffffffff, 0x00000c00);
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halrf_wreg(rf, 0x8018, 0xfffffffe, 0x20008080);
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halrf_wreg(rf, 0x80d0, 0xffffffff, 0x00300000);
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if (psd_info->path == RF_PATH_A)
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halrf_wreg(rf, 0x81cc, 0x0000003f, 0x3f);
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else
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halrf_wreg(rf, 0x82cc, 0x0000003f, 0x3f);
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halrf_wreg(rf, 0x802c, 0x0fff0000, (point & 0xfff));
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halrf_wreg(rf, 0x8034, 0x00000001, 0x1);
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halrf_wreg(rf, 0x8034, 0x00000001, 0x0);
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halrf_delay_ms(rf, 1);
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halrf_wreg(rf, 0x80d4, 0xffffffff, 0x002d0000);
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val_tmp = halrf_rreg(rf, 0x80fc, 0x007f0000);
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halrf_wreg(rf, 0x80d4, 0xffffffff, 0x002e0000);
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val = halrf_rreg(rf, 0x80fc, 0xffffffff);
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data = (val_tmp << 25) | (val >> 7);
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RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d point=0x%x data=0x%08x\n",
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__func__, phy, point, data);
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return data;
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}
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void halrf_psd_query_8852b(struct rf_info *rf, enum phl_phy_idx phy,
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u32 point, u32 start_point, u32 stop_point, u32 *outbuf)
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{
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struct halrf_psd_data *psd_info = &rf->psd;
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struct rtw_hal_com_t *hal = rf->hal_com;
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u32 i = 0, j = 0;
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s32 point_temp;
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RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d point=%d start_point=%d stop_point=%d\n",
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__func__, phy, point, start_point, stop_point);
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if (psd_info->psd_result_running == true) {
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RF_DBG(rf, DBG_RF_PSD, "======> %s PSD Running Return !!!\n", __func__);
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return;
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}
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psd_info->psd_result_running = true;
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hal_mem_set(hal, psd_info->psd_data, 0, sizeof(psd_info->psd_data));
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i = start_point;
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while (i < stop_point) {
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if (i >= point)
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point_temp = i - point;
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else
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{
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point_temp = i - point;
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point_temp = point_temp & 0xfff;
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}
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psd_info->psd_data[j] = halrf_psd_get_point_data_8852b(rf, phy, point_temp);
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i++;
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j++;
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}
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RF_DBG(rf, DBG_RF_PSD, "psd_info->psd_data\n");
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for (i = 0; i < 320; i = i + 10) {
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RF_DBG(rf, DBG_RF_PSD, "%d %d %d %d %d %d %d %d %d %d\n",
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psd_info->psd_data[i], psd_info->psd_data[i + 1],
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psd_info->psd_data[i + 2], psd_info->psd_data[i + 3],
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psd_info->psd_data[i + 4], psd_info->psd_data[i + 5],
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psd_info->psd_data[i + 6], psd_info->psd_data[i + 7],
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psd_info->psd_data[i + 8], psd_info->psd_data[i + 9]);
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}
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hal_mem_cpy(hal, outbuf, psd_info->psd_data,
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sizeof(psd_info->psd_data));
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RF_DBG(rf, DBG_RF_PSD, "======> %s PSD End !!!\n", __func__);
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psd_info->psd_result_running = false;
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}
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#endif /*RF_8852B_SUPPORT*/
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