/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALRF_H__
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#define __HALRF_H__
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/*@--------------------------[Define] ---------------------------------------*/
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/*H2C cmd ID*/
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/*Class 8*/
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/*Class 9*/
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/*Class a*/
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#define FWCMD_H2C_BACKUP_RFK 0
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#define FWCMD_H2C_RELOAD_RFK 1
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#define FWCMD_H2C_GET_MCCCH 2
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#define FWCMD_H2C_DPK_OFFLOAD 3
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#define FWCMD_H2C_IQK_OFFLOAD 4
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/*@--------------------------[Enum]------------------------------------------*/
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enum halrf_func_idx {
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RF00_PWR_TRK = 0,
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RF01_IQK = 1,
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RF02_LCK = 2,
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RF03_DPK = 3,
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RF04_TXGAPK = 4,
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RF05_DACK = 5,
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RF06_DPK_TRK = 6,
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RF07_2GBAND_SHIFT = 7,
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RF08_RXDCK = 8,
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RF09_RFK = 9,
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RF10_RF_INIT = 10,
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RF11_RF_POWER = 11,
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RF12_RXGAINK = 12,
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RF13_THER_TRIM = 13,
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RF14_PABIAS_TRIM = 14,
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RF15_TSSI_TRIM = 15,
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RF16_PSD = 16,
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RF17_TSSI_TRK = 17,
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RF18_XTAL_TRK = 18,
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RF19_TX_SHAPE = 19
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};
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enum halrf_rf_mode {
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RF_SHUT_DOWN = 0x0,
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RF_STANDBY = 0x1,
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RF_TX = 0x2,
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RF_RX = 0x3,
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RF_TXIQK = 0x4,
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RF_DPK = 0x5,
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RF_RXK1 = 0x6,
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RF_RXK2 = 0x7
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};
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enum halrf_rfe_src_sel {
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HALRF_PAPE_RFM = 0,
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HALRF_GNT_BT_INV = 1,
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HALRF_LNA0N = 2,
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HALRF_LNAON_RFM = 3,
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HALRF_TRSW_RFM = 4,
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HALRF_TRSW_RFM_B = 5,
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HALRF_GNT_BT = 6,
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HALRF_ZERO = 7,
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HALRF_ANTSEL_0 = 8,
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HALRF_ANTSEL_1 = 9,
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HALRF_ANTSEL_2 = 0xa,
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HALRF_ANTSEL_3 = 0xb,
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HALRF_ANTSEL_4 = 0xc,
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HALRF_ANTSEL_5 = 0xd,
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HALRF_ANTSEL_6 = 0xe,
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HALRF_ANTSEL_7 = 0xf
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};
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/*@=[HALRF supportability]=======================================*/
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enum halrf_ability {
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HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
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HAL_RF_IQK = BIT(RF01_IQK),
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HAL_RF_LCK = BIT(RF02_LCK),
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HAL_RF_DPK = BIT(RF03_DPK),
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HAL_RF_TXGAPK = BIT(RF04_TXGAPK),
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HAL_RF_DACK = BIT(RF05_DACK),
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HAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
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HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT),
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HAL_RF_RXDCK = BIT(RF08_RXDCK),
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HAL_RF_RXGAINK = BIT(RF12_RXGAINK),
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HAL_RF_THER_TRIM = BIT(RF13_THER_TRIM),
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HAL_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM),
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HAL_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM),
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HAL_RF_TSSI_TRK = BIT(RF17_TSSI_TRK),
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HAL_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK),
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HAL_RF_TX_SHAPE = BIT(RF19_TX_SHAPE)
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};
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/*@=[HALRF Debug Component]=====================================*/
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enum halrf_dbg_comp {
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DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
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DBG_RF_IQK = BIT(RF01_IQK),
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DBG_RF_LCK = BIT(RF02_LCK),
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DBG_RF_DPK = BIT(RF03_DPK),
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DBG_RF_TXGAPK = BIT(RF04_TXGAPK),
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DBG_RF_DACK = BIT(RF05_DACK),
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DBG_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
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DBG_RF_RXDCK = BIT(RF08_RXDCK),
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DBG_RF_RFK = BIT(RF09_RFK),
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DBG_RF_INIT = BIT(RF10_RF_INIT),
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DBG_RF_POWER = BIT(RF11_RF_POWER),
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DBG_RF_RXGAINK = BIT(RF12_RXGAINK),
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DBG_RF_THER_TRIM = BIT(RF13_THER_TRIM),
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DBG_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM),
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DBG_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM),
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DBG_RF_PSD = BIT(RF16_PSD),
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DBG_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK),
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DBG_RF_FW = BIT(28),
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DBG_RF_MP = BIT(29),
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DBG_RF_TMP = BIT(30),
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DBG_RF_CHK = BIT(31)
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct rfk_location {
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enum band_type cur_band;
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enum channel_width cur_bw;
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u8 cur_ch;
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};
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struct halrf_fem_info {
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u8 elna_2g; /*@with 2G eLNA NO/Yes = 0/1*/
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u8 elna_5g; /*@with 5G eLNA NO/Yes = 0/1*/
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u8 elna_6g; /*@with 6G eLNA NO/Yes = 0/1*/
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u8 epa_2g; /*@with 2G ePA NO/Yes = 0/1*/
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u8 epa_5g; /*@with 5G ePA NO/Yes = 0/1*/
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u8 epa_6g; /*@with 6G ePA NO/Yes = 0/1*/
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};
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#if 1 /* all rf operation usage (header) */
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/* clang-format on */
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#define RF_PATH_MAX_NUM (8)
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#define RF_TASK_RECORD_MAX_TIMES (16)
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#define RF_BACKUP_MAC_REG_MAX_NUM (16)
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#define RF_BACKUP_BB_REG_MAX_NUM (16)
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#define RF_BACKUP_RF_REG_MAX_NUM (16)
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struct halrf_iqk_ops {
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u8 (*iqk_kpath)(struct rf_info *rf, enum phl_phy_idx phy_idx);
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bool (*iqk_mcc_page_sel)(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
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void (*iqk_get_ch_info)(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
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void (*iqk_preset)(struct rf_info *rf, u8 path);
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void (*iqk_macbb_setting)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
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void (*iqk_start_iqk)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
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void (*iqk_restore)(struct rf_info *rf, u8 path);
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void (*iqk_afebb_restore)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
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};
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struct rfk_iqk_info {
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struct halrf_iqk_ops *rf_iqk_ops;
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u8 rf_max_path_num;
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u32 rf_iqk_version;
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u8 rf_iqk_ch_num;
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u8 rf_iqk_path_num;
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const u32 *backup_mac_reg;
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u32 backup_mac_reg_num;
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const u32 *backup_bb_reg;
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u32 backup_bb_reg_num;
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const u32 *backup_rf_reg;
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u32 backup_rf_reg_num;
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};
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/* clang-format off */
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#endif /* all rf operation usage (header) */
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#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
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struct halrf_fw_offload {
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enum rtw_mac_src_cmd_ofld src;
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enum rtw_mac_cmd_type_ofld type;
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u8 lc;
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enum rtw_mac_rf_path rf_path;
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u16 offset;
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u16 id;
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u32 value;
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u32 mask;
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};
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#endif
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struct halrf_rx_dck_info {
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bool is_afe;
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struct rfk_location loc[KPATH]; /*max RF path*/
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};
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struct rf_info {
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struct rtw_phl_com_t *phl_com;
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struct rtw_hal_com_t *hal_com;
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/*[Common Info]*/
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u32 ic_type;
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u8 num_rf_path;
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/*[System Info]*/
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bool rf_init_ready;
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u32 rf_sys_up_time;
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bool rf_watchdog_en;
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bool rf_ic_api_en;
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/*[DM Info]*/
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u32 support_ability;
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u32 manual_support_ability;
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/*[FW Info]*/
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u32 fw_dbg_component;
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/*[Drv Dbg Info]*/
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u32 dbg_component;
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u8 cmn_dbg_msg_period;
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u8 cmn_dbg_msg_cnt;
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/*[BTC / RFK Info ]*/
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bool rfk_is_processing;
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bool is_bt_iqk_timeout;
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/*[initial]*/
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u8 pre_rxbb_bw[KPATH];
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/*[TSSI Info]*/
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bool is_tssi_mode[4]; /*S0/S1*/
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/*[Thermal Trigger]*/
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bool is_thermal_trigger;
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/*[Do Coex]*/
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bool is_coex;
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/*[watchdog]*/
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bool is_watchdog_stop;
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/*[thermal rek indictor]*/
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bool rfk_do_thr_rek;
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/*reg check*/
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u32 rfk_reg[2048];
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u32 rfc_reg[2][10];
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u32 rfk_check_fail_count;
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/*fast channel switch*/
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u8 ther_init;
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u32 fcs_rfk_ok_map;
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u8 pre_chl_idx;
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u8 pre_ther_idx;
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/* [Check NCTL Done status Read Times] */
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u32 nctl_ck_times[2]; /* 0xbff8 0x80fc*/
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u32 fw_ofld_enable;
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/*@=== [HALRF Structure] ============================================*/
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struct halrf_pwr_track_info pwr_track;
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struct halrf_tssi_info tssi;
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struct halrf_xtal_info xtal_track;
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struct halrf_iqk_info iqk;
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struct halrf_dpk_info dpk;
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struct halrf_rx_dck_info rx_dck;
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struct halrf_dack_info dack;
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struct halrf_gapk_info gapk;
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struct halrf_pwr_info pwr_info;
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struct halrf_radio_info radio_info;
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struct halrf_fem_info fem;
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struct rf_dbg_cmd_info rf_dbg_cmd_i;
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struct halrf_kfree_info kfree_info;
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struct halrf_psd_data psd;
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struct rfk_location iqk_loc[2]; /*S0/S1*/
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struct rfk_location dpk_loc[2]; /*S0/S1*/
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struct rfk_location gapk_loc[2]; /*S0/S1*/
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struct rfk_iqk_info *rfk_iqk_info;
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#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
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struct halrf_fw_offload fwofld;
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#endif
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};
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/*@--------------------------[Prptotype]-------------------------------------*/
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#endif
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