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/******************************************************************************
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*
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* Copyright(c) 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _PHL_DM_C_
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#include "phl_headers.h"
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void rtw_phl_set_edcca_mode(void *phl, enum rtw_edcca_mode mode)
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{
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struct phl_info_t *phl_info = (struct phl_info_t *)phl;
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PHL_INFO("[Cert], set phl_com edcca_mode : %d !! \n", mode);
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phl_info->phl_com->edcca_mode = mode;
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}
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enum rtw_edcca_mode rtw_phl_get_edcca_mode(void *phl)
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{
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struct phl_info_t *phl_info = (struct phl_info_t *)phl;
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return phl_info->phl_com->edcca_mode;
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}
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#ifdef CONFIG_PCI_HCI
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#ifdef RTW_WKARD_DYNAMIC_LTR
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enum rtw_phl_status
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phl_ltr_sw_trigger(struct rtw_phl_com_t *phl_com, void *hal,
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enum rtw_pcie_ltr_state state)
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{
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enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
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struct bus_sw_cap_t *sw_cap = &phl_com->bus_sw_cap;
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status = rtw_hal_ltr_sw_trigger(hal, state);
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if (status == RTW_HAL_STATUS_SUCCESS) {
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sw_cap->ltr_cur_state = state;
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sw_cap->ltr_last_trigger_time = _os_get_cur_time_us();
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state == RTW_PCIE_LTR_SW_ACT ?
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sw_cap->ltr_sw_act_tri_cnt++ : sw_cap->ltr_sw_idle_tri_cnt++;
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return RTW_PHL_STATUS_SUCCESS;
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} else {
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return RTW_PHL_STATUS_FAILURE;
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}
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}
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/* Switching sw ctrl will trigger active ltr at the same time
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to prevent inconsistent state */
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/* usage : echo phl ltr set [enable/disable] */
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enum rtw_phl_status
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phl_ltr_sw_ctrl(struct rtw_phl_com_t *phl_com, void *hal, bool enable)
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{
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enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
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status = phl_ltr_sw_trigger(phl_com, hal, RTW_PCIE_LTR_SW_ACT);
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if (status == RTW_HAL_STATUS_SUCCESS) {
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phl_com->bus_sw_cap.ltr_sw_ctrl = enable;
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return RTW_PHL_STATUS_SUCCESS;
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} else {
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return RTW_PHL_STATUS_FAILURE;
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}
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}
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/* switch to hw control. it's valid that only hw supports hw mode */
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/* usage : echo phl ltr set [enable/disable] */
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void
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phl_ltr_hw_ctrl(struct rtw_phl_com_t *phl_com, bool enable)
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{
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phl_com->bus_sw_cap.ltr_hw_ctrl = enable;
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}
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/* For pm module, this will not trigger active ltr since halmac will take care of*/
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void phl_ltr_sw_ctrl_ntfy(struct rtw_phl_com_t *phl_com, bool enable)
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{
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phl_com->bus_sw_cap.ltr_sw_ctrl = enable;
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}
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u8 phl_ltr_get_cur_state(struct rtw_phl_com_t *phl_com)
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{
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return phl_com->bus_sw_cap.ltr_cur_state;
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}
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u32 phl_ltr_get_last_trigger_time(struct rtw_phl_com_t *phl_com)
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{
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return phl_com->bus_sw_cap.ltr_last_trigger_time;
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}
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u32 phl_ltr_get_tri_cnt(struct rtw_phl_com_t *phl_com,
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enum rtw_pcie_ltr_state state)
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{
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struct bus_sw_cap_t *sw_cap = &phl_com->bus_sw_cap;
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return state == RTW_PCIE_LTR_SW_ACT ?
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sw_cap->ltr_sw_act_tri_cnt : sw_cap->ltr_sw_idle_tri_cnt;
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}
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#define TP_MBPS 100
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void phl_ltr_ctrl_watchdog(struct phl_info_t *phl_info)
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{
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struct rtw_phl_com_t *phl_com = phl_info->phl_com;
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struct rtw_stats *sts = &phl_com->phl_stats;
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u32 tx_tp_m = 0, rx_tp_m = 0;
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static bool start = false;
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/* only valid if it's currenlty running hw mode */
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if (!rtw_hal_ltr_is_hw_ctrl(phl_com, phl_info->hal))
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return;
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tx_tp_m = sts->tx_tp_kbits >> 10;
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rx_tp_m = sts->rx_tp_kbits >> 10;
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/* PHL_INFO("%s tx_tp_m = %u /rx_tp_m = %u \n", __func__, tx_tp_m, rx_tp_m);*/
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if ((tx_tp_m > TP_MBPS || rx_tp_m > TP_MBPS) && !start) {
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start = true;
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rtw_hal_ltr_en_hw_mode(phl_info->hal, false);
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rtw_hal_ltr_sw_trigger(phl_info->hal, RTW_PCIE_LTR_SW_ACT);
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}
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if (start && tx_tp_m < TP_MBPS && rx_tp_m < TP_MBPS) {
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start = false;
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rtw_hal_ltr_en_hw_mode(phl_info->hal, true);
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}
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}
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#endif /* RTW_WKARD_DYNAMIC_LTR */
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#endif /* CONFIG_PCI_HCI */
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