/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#include "../halrf_precomp.h"
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#ifdef RF_8852B_SUPPORT
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#define t_avg 100
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void halrf_afe_init_8852b(struct rf_info *rf)
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{
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halrf_wmac32(rf, 0x8040, 0xf);
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halrf_wreg(rf, 0xc0d4, MASKDWORD, 0x4486888c);
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halrf_wreg(rf, 0xc0d8, MASKDWORD, 0xc6ba10e0);
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halrf_wreg(rf, 0xc0dc, MASKDWORD, 0x30c52868);
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halrf_wreg(rf, 0xc0e0, MASKDWORD, 0x05008128);
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halrf_wreg(rf, 0xc0e4, MASKDWORD, 0x0000272b);
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halrf_wreg(rf, 0xc1d4, MASKDWORD, 0x4486888c);
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halrf_wreg(rf, 0xc1d8, MASKDWORD, 0xc6ba10e0);
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halrf_wreg(rf, 0xc1dc, MASKDWORD, 0x30c52868);
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halrf_wreg(rf, 0xc1e0, MASKDWORD, 0x05008128);
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halrf_wreg(rf, 0xc1e4, MASKDWORD, 0x0000272b);
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}
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void halrf_dack_init_8852b(struct rf_info *rf)
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{
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}
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void halrf_drck_8852b(struct rf_info *rf)
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{
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u32 c;
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u32 rck_d;
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RF_DBG(rf, DBG_RF_DACK, "[DACK]Ddie RCK start!!!\n");
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halrf_wreg(rf, 0xc0cc, BIT(6), 0x1);
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c = 0;
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while (halrf_rreg(rf, 0xc0d0, BIT(3)) == 0) {
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c++;
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halrf_delay_us(rf, 1);
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if (c > 10000) {
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RF_DBG(rf, DBG_RF_DACK, "[DACK]DRCK timeout\n");
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break;
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}
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}
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halrf_wreg(rf, 0xc0cc, BIT(6), 0x0);
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halrf_wreg(rf, 0xc094, BIT(9), 0x1);
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halrf_delay_us(rf, 1);
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halrf_wreg(rf, 0xc094, BIT(9), 0x0);
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/*manual write for LPS*/
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rck_d = halrf_rreg(rf, 0xc0d0, 0xf8000);
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/*RCK_SEL=0*/
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halrf_wreg(rf, 0xc0cc, BIT(9), 0x0);
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halrf_wreg(rf, 0xc0cc, 0x1f, rck_d);
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RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc0cc = 0x%x\n", halrf_rreg(rf, 0xc0cc, MASKDWORD));
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}
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void halrf_addck_backup_8852b(struct rf_info *rf)
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{
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struct halrf_dack_info *dack = &rf->dack;
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halrf_wreg(rf, 0xc0f4, 0x300, 0x0);
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dack->addck_d[0][0] = (u16)halrf_rreg(rf, 0xc0fc,0xffc00) ;
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dack->addck_d[0][1] = (u16)halrf_rreg(rf, 0xc0fc,0x003ff) ;
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halrf_wreg(rf, 0xc1f4, 0x300, 0x0);
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dack->addck_d[1][0] = (u16)halrf_rreg(rf, 0xc1fc,0xffc00) ;
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dack->addck_d[1][1] = (u16)halrf_rreg(rf, 0xc1fc,0x003ff) ;
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}
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void halrf_addck_reload_8852b(struct rf_info *rf)
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{
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struct halrf_dack_info *dack = &rf->dack;
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/*S0*/
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halrf_wreg(rf, 0xc0f0, 0x3ff0000, dack->addck_d[0][0]);
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halrf_wreg(rf, 0xc0f4, 0xf, (dack->addck_d[0][1] >> 6));
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halrf_wreg(rf, 0xc0f0, 0xfc000000, (dack->addck_d[0][1] & 0x3f));
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/*manual*/
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halrf_wreg(rf, 0xc0f4, 0x30, 0x3);
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/*S1*/
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halrf_wreg(rf, 0xc1f0, 0x3ff0000, dack->addck_d[1][0]);
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halrf_wreg(rf, 0xc1f4, 0xf, (dack->addck_d[1][1] >> 6));
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halrf_wreg(rf, 0xc1f0, 0xfc000000, (dack->addck_d[1][1] & 0x3f));
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/*manual*/
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halrf_wreg(rf, 0xc1f4, 0x30, 0x3);
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}
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void halrf_dack_backup_s0_8852b(struct rf_info *rf)
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{
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struct halrf_dack_info *dack = &rf->dack;
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u8 i;
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// u32 temp;
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// halrf_wreg(rf, 0x5e00, BIT(3), 0x1);
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// halrf_wreg(rf, 0x5e50, BIT(3), 0x1);
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halrf_wreg(rf, 0x12b8, BIT(30), 0x1);
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/*MSBK*/
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#if 0
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for (i = 0; i < 0x10; i++) {
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/*S0*/
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halrf_wreg(rf, 0xc000, 0x1e, i);
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temp = (u8)halrf_rreg(rf, 0xc04c, 0x7fc0);
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RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc04c %d = 0x%x\n",
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i, temp);
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}
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for (i = 0; i < 0x10; i++) {
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/*S0*/
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halrf_wreg(rf, 0xc020, 0x1e, i);
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temp = (u8)halrf_rreg(rf, 0xc070, 0x7fc0);
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RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc070 %d = 0x%x\n",
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i, temp);
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}
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#endif
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for (i = 0; i < 0x10; i++) {
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/*S0*/
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halrf_wreg(rf, 0xc000, 0x1e, i);
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dack->msbk_d[0][0][i] = (u8)halrf_rreg(rf, 0xc05c, 0xff000000);
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halrf_wreg(rf, 0xc020, 0x1e, i);
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dack->msbk_d[0][1][i] = (u8)halrf_rreg(rf, 0xc080, 0xff000000);
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}
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/*biasK*/
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dack->biask_d[0][0] = (u16)halrf_rreg(rf, 0xc048, 0xffc);
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dack->biask_d[0][1] = (u16)halrf_rreg(rf, 0xc06c, 0xffc);
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/*DADCK*/
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dack->dadck_d[0][0] = (u8)halrf_rreg(rf, 0xc060, 0xff000000);
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dack->dadck_d[0][1] = (u8)halrf_rreg(rf, 0xc084, 0xff000000);
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}
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void halrf_dack_backup_s1_8852b(struct rf_info *rf)
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{
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struct halrf_dack_info *dack = &rf->dack;
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u8 i;
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// u32 temp;
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// halrf_wreg(rf, 0x7e00, BIT(3), 0x1);
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// halrf_wreg(rf, 0x7e50, BIT(3), 0x1);
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halrf_wreg(rf, 0x32b8, BIT(30), 0x1);
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/*MSBK*/
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#if 0
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for (i = 0; i < 0x10; i++) {
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/*S0*/
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halrf_wreg(rf, 0xc100, 0x1e, i);
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temp = (u8)halrf_rreg(rf, 0xc14c, 0x7fc0);
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RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc14c %d = 0x%x\n",
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i, temp);
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}
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for (i = 0; i < 0x10; i++) {
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/*S0*/
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halrf_wreg(rf, 0xc120, 0x1e, i);
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temp = (u8)halrf_rreg(rf, 0xc170, 0x7fc0);
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RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc170 %d = 0x%x\n",
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i, temp);
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}
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#endif
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for (i = 0; i < 0x10; i++) {
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/*S1*/
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halrf_wreg(rf, 0xc100, 0x1e, i);
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dack->msbk_d[1][0][i] = (u8)halrf_rreg(rf, 0xc15c, 0xff000000);
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halrf_wreg(rf, 0xc120, 0x1e, i);
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dack->msbk_d[1][1][i] = (u8)halrf_rreg(rf, 0xc180, 0xff000000);
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}
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/*biasK*/
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dack->biask_d[1][0] = (u16)halrf_rreg(rf, 0xc148, 0xffc);
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dack->biask_d[1][1] = (u16)halrf_rreg(rf, 0xc16c, 0xffc);
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/*DADCK*/
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dack->dadck_d[1][0] = (u8)halrf_rreg(rf, 0xc160, 0xff000000);
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dack->dadck_d[1][1] = (u8)halrf_rreg(rf, 0xc184, 0xff000000);
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}
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void halrf_dack_reload_by_path_8852b(struct rf_info *rf, enum rf_path path)
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{
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struct halrf_dack_info *dack = &rf->dack;
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u8 i;
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u32 oft;
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if (path == RF_PATH_A)
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oft = 0;
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else
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oft = 0x100;
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/*MSBK*/
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for (i = 0; i < 16; i++) {
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halrf_wreg(rf, 0xc000+ oft, 0x1e, i);
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halrf_wreg(rf, 0xc004+ oft, 0x3fc0, dack->msbk_d[path][0][i]);
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}
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for (i = 0; i < 16; i++) {
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halrf_wreg(rf, 0xc020+ oft, 0x1e, i);
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halrf_wreg(rf, 0xc024+ oft, 0x3fc0, dack->msbk_d[path][1][i]);
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}
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/*biask*/
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halrf_wreg(rf, 0xc004+ oft, 0x3ff00000, dack->biask_d[path][0]);
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halrf_wreg(rf, 0xc024+ oft, 0x3ff00000, dack->biask_d[path][1]);
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/*DADCK*/
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}
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void halrf_dack_reload_8852b(struct rf_info *rf, enum rf_path path)
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{
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u32 oft;
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if (path == RF_PATH_A)
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oft = 0;
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else
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oft = 0x100;
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halrf_wreg(rf, 0xc004 + oft, 0x3, 0x2);
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halrf_wreg(rf, 0xc024 + oft, 0x3, 0x2);
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halrf_wreg(rf, 0xc004 + oft, BIT(5), 0x1);
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halrf_wreg(rf, 0xc024 + oft, BIT(5), 0x1);
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halrf_dack_reload_by_path_8852b(rf, path);
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halrf_wreg(rf, 0xc004 + oft, 0x3, 0x0);
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halrf_wreg(rf, 0xc024 + oft, 0x3, 0x0);
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}
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void halrf_check_addc_8852b(struct rf_info *rf, enum rf_path path)
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{
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u32 temp, dc_re, dc_im;
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u32 i, m, p, t;
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u32 re[t_avg], im[t_avg];
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#if 1
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halrf_wreg(rf, 0x20f4, BIT(24), 0x0);
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halrf_wreg(rf, 0x20f8, 0x80000000, 0x1);
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halrf_wreg(rf, 0x20f0, 0xff0000, 0x1);
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halrf_wreg(rf, 0x20f0, 0xf00, 0x2);
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halrf_wreg(rf, 0x20f0, 0xf, 0x0);
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if (path == RF_PATH_A)
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halrf_wreg(rf, 0x20f0, 0xc0, 0x2);
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else
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halrf_wreg(rf, 0x20f0, 0xc0, 0x3);
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for (i = 0; i < t_avg; i++) {
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temp = halrf_rreg(rf, 0x1730, 0xffffffff);
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re[i] = (temp & 0xfff000) >> 12;
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im[i] = temp & 0xfff;
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// RF_DBG(rf, DBG_RF_DACK, "[DACK]S%d,re[i]= 0x%x,im[i] =0x%x\n",
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// path, re[i], im[i]);
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}
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#else
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for (i = 0; i < t_avg; i++) {
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if (path == RF_PATH_A)
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temp = halrf_rreg(rf, 0x1c8c, MASKDWORD);
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else
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temp = halrf_rreg(rf, 0x3c8c, MASKDWORD);
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re[i] = (temp & 0xfff000) >> 12;
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im[i] = temp & 0xfff;
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// RF_DBG(rf, DBG_RF_DACK, "[DACK]S%d,re[i]= 0x%x,im[i] =0x%x\n",
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// path, re[i], im[i]);
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}
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#endif
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m = 0;
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p = 0;
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for (i = 0; i < t_avg; i++) {
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if (re[i] > 0x800)
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m = (0x1000 - re[i]) + m;
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else
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p = re[i] + p;
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}
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if (p > m) {
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t = p - m;
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t = t / t_avg;
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} else {
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t = m - p;
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t = t / t_avg;
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if (t != 0x0)
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t = 0x1000 - t;
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}
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dc_re = t;
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m = 0;
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p = 0;
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for (i = 0; i < t_avg; i++) {
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if (im[i] > 0x800)
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m = (0x1000 - im[i]) + m;
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else
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p = im[i] + p;
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}
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if (p > m) {
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t = p - m;
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t = t / t_avg;
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} else {
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t = m - p;
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t = t / t_avg;
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if (t != 0x0)
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t = 0x1000 - t;
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}
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dc_im = t;
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RF_DBG(rf, DBG_RF_DACK, "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n",
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path, dc_re, dc_im);
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}
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void halrf_addck_8852b(struct rf_info *rf)
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{
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struct halrf_dack_info *dack = &rf->dack;
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u32 c;
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/*S0*/
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#if 1
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/*manual off*/
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halrf_wreg(rf, 0xc0f4, 0x30, 0x0);
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halrf_wreg(rf, 0xc1d4, 0x30, 0x0);
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/*1.ADC & clk enable */
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halrf_wreg(rf, 0x12b8, BIT(30), 0x1);
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halrf_wreg(rf, 0x032c, BIT(30), 0x0);
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/*4.Reset calibration*/
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halrf_wreg(rf, 0x032c, BIT(22), 0x0);
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halrf_wreg(rf, 0x032c, BIT(22), 0x1);
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halrf_wreg(rf, 0x030c, 0x0f000000, 0xf);
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/*2.ADC input not from RXBB & ADC input short*/
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halrf_wreg(rf, 0x032c, BIT(16), 0x0);
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halrf_wreg(rf, 0xc0d4, BIT(1), 0x1);
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/*3.release ADC reset*/
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halrf_wreg(rf, 0x030c, 0x0f000000, 0x3);
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RF_DBG(rf, DBG_RF_DACK, "[DACK]before S0 ADDCK\n");
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halrf_check_addc_8852b(rf, RF_PATH_A);
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/*average 128 times*/
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// halrf_wreg(rf, 0xc0f4, BIT(7) | BIT(6), 0x3);
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/*5.trigger dc offset calibration*/
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halrf_wreg(rf, 0xc0f4, BIT(11), 0x1);
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halrf_wreg(rf, 0xc0f4, BIT(11), 0x0);
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halrf_delay_us(rf, 1);
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/*check if cal done*/
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halrf_wreg(rf, 0xc0f4, 0x300, 0x1);
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c = 0;
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while (halrf_rreg(rf, 0xc0fc, BIT(0)) == 0) {
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c++;
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halrf_delay_us(rf, 1);
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if (c > 10000) {
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RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 ADDCK timeout\n");
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dack->addck_timeout[0] = true;
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break;
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}
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}
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RF_DBG(rf, DBG_RF_DACK, "[DACK]ADDCK c = %d\n", c);
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RF_DBG(rf, DBG_RF_DACK, "[DACK]after S0 ADDCK\n");
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halrf_check_addc_8852b(rf, RF_PATH_A);
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/*restore*/
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halrf_wreg(rf, 0xc0d4, BIT(1), 0x0);
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halrf_wreg(rf, 0x032c, BIT(16), 0x1);
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halrf_wreg(rf, 0x030c, 0x0f000000, 0xc);
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halrf_wreg(rf, 0x032c, BIT(30), 0x1);
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halrf_wreg(rf, 0x12b8, BIT(30), 0x0);
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#endif
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/*S1*/
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#if 1
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/*1.ADC & clk enable */
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halrf_wreg(rf, 0x32b8, BIT(30), 0x1);
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halrf_wreg(rf, 0x032c, BIT(30), 0x0);
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/*4.Reset calibration*/
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halrf_wreg(rf, 0x032c, BIT(22), 0x0);
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halrf_wreg(rf, 0x032c, BIT(22), 0x1);
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halrf_wreg(rf, 0x030c, 0x0f000000, 0xf);
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/*2.ADC input not from RXBB & ADC input short*/
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halrf_wreg(rf, 0x032c, BIT(16), 0x0);
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halrf_wreg(rf, 0xc1d4, BIT(1), 0x1);
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/*3.release ADC reset*/
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halrf_wreg(rf, 0x030c, 0x0f000000, 0x3);
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RF_DBG(rf, DBG_RF_DACK, "[DACK]before S1 ADDCK\n");
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halrf_check_addc_8852b(rf, RF_PATH_B);
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/*average 128 times*/
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// halrf_wreg(rf, 0xc1f4, BIT(7) | BIT(6), 0x3);
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/*5.trigger dc offset calibration*/
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halrf_wreg(rf, 0xc1f4, BIT(11), 0x1);
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halrf_wreg(rf, 0xc1f4, BIT(11), 0x0);
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halrf_delay_us(rf, 1);
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/*check if cal done*/
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halrf_wreg(rf, 0xc1f4, 0x300, 0x1);
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c = 0;
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while (halrf_rreg(rf, 0xc1fc, BIT(0)) == 0) {
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c++;
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halrf_delay_us(rf, 1);
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if (c > 10000) {
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RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 ADDCK timeout\n");
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dack->addck_timeout[1] = true;
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break;
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}
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}
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RF_DBG(rf, DBG_RF_DACK, "[DACK]ADDCK c = %d\n", c);
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RF_DBG(rf, DBG_RF_DACK, "[DACK]after S1 ADDCK\n");
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halrf_check_addc_8852b(rf, RF_PATH_B);
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/*restore*/
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halrf_wreg(rf, 0xc1d4, BIT(1), 0x0);
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halrf_wreg(rf, 0x032c, BIT(16), 0x1);
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halrf_wreg(rf, 0x030c, 0x0f000000, 0xc);
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halrf_wreg(rf, 0x032c, BIT(30), 0x1);
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halrf_wreg(rf, 0x32b8, BIT(30), 0x0);
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#endif
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}
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void halrf_check_dadc_8852b(struct rf_info *rf, enum rf_path path)
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{
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halrf_wreg(rf, 0x032c, BIT(30), 0x0);
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halrf_wreg(rf, 0x030c, 0x0f000000, 0xf);
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halrf_wreg(rf, 0x030c, 0x0f000000, 0x3);
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halrf_wreg(rf, 0x032c, BIT(16), 0x0);
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if (path == RF_PATH_A) {
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halrf_wreg(rf, 0x12dc, BIT(0), 0x1);
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halrf_wreg(rf, 0x12e8, BIT(2), 0x1);
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halrf_wrf(rf, RF_PATH_A, 0x8f, BIT(13), 0x1);
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} else {
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halrf_wreg(rf, 0x32dc, BIT(0), 0x1);
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halrf_wreg(rf, 0x32e8, BIT(2), 0x1);
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halrf_wrf(rf, RF_PATH_B, 0x8f, BIT(13), 0x1);
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}
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halrf_check_addc_8852b(rf, path);
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if (path == RF_PATH_A) {
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halrf_wreg(rf, 0x12dc, BIT(0), 0x0);
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halrf_wreg(rf, 0x12e8, BIT(2), 0x0);
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halrf_wrf(rf, RF_PATH_A, 0x8f, BIT(13), 0x0);
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} else {
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halrf_wreg(rf, 0x32dc, BIT(0), 0x0);
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halrf_wreg(rf, 0x32e8, BIT(2), 0x0);
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halrf_wrf(rf, RF_PATH_B, 0x8f, BIT(13), 0x0);
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}
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halrf_wreg(rf, 0x032c, BIT(16), 0x1);
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}
|
|
void halrf_dack_8852b_s0(struct rf_info *rf)
|
{
|
struct halrf_dack_info *dack = &rf->dack;
|
u32 c = 0;
|
|
/*step 1*/
|
halrf_wreg(rf, 0x12a0, BIT(15), 0x1);
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halrf_wreg(rf, 0x12a0, 0x7000, 0x3);
|
/*step 2*/
|
halrf_wreg(rf, 0x12b8, BIT(30), 0x1);
|
halrf_wreg(rf, 0x030c, BIT(28), 0x1);
|
halrf_wreg(rf, 0x032c, 0x80000000, 0x0);
|
/*step 3*/
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halrf_wreg(rf, 0xc0d8, BIT(16), 0x1);
|
/*step 4*/
|
halrf_wreg(rf, 0xc0dc, BIT(27) | BIT(26), 0x3);
|
/*step 5*/
|
halrf_wreg(rf, 0xc004, BIT(30), 0x0);
|
halrf_wreg(rf, 0xc024, BIT(30), 0x0);
|
/*step 6*/
|
halrf_wreg(rf, 0xc004, 0x3ff00000, 0x30);
|
// halrf_wreg(rf, 0xc024, 0x3ff00000, 0x30);
|
/*step 7*/
|
halrf_wreg(rf, 0xc004, BIT(31) | BIT(30), 0x0);
|
// halrf_wreg(rf, 0xc024, BIT(31) | BIT(30), 0x0);
|
/*step 8*/
|
halrf_wreg(rf, 0xc004, BIT(17), 0x1);
|
halrf_wreg(rf, 0xc024, BIT(17), 0x1);
|
halrf_wreg(rf, 0xc00c, BIT(2), 0x0);
|
halrf_wreg(rf, 0xc02c, BIT(2), 0x0);
|
/*step 9*/ /*auto mode*/
|
halrf_wreg(rf, 0xc004, BIT(0), 0x1);
|
halrf_wreg(rf, 0xc024, BIT(0), 0x1);
|
halrf_delay_us(rf, 1);
|
/*step 10*/
|
c = 0x0;
|
while ((halrf_rreg(rf, 0xc040, BIT(31)) == 0) || (halrf_rreg(rf, 0xc064, BIT(31)) == 0)) {
|
c++;
|
halrf_delay_us(rf, 1);
|
if (c > 10000) {
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 MSBK timeout\n");
|
dack->msbk_timeout[0] = true;
|
break;
|
}
|
}
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c);
|
/*step 11*/
|
halrf_wreg(rf, 0xc0dc, BIT(27) | BIT(26), 0x0);
|
/*step 12*/
|
halrf_wreg(rf, 0xc00c, BIT(2), 0x1);
|
halrf_wreg(rf, 0xc02c, BIT(2), 0x1);
|
/*step 13*/
|
c = 0x0;
|
while ((halrf_rreg(rf, 0xc05c, BIT(2)) == 0) || (halrf_rreg(rf, 0xc080, BIT(2)) == 0)) {
|
c++;
|
halrf_delay_us(rf, 1);
|
if (c > 10000) {
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 DADCK timeout\n");
|
dack->dadck_timeout[0] = true;
|
break;
|
}
|
}
|
/*step 14*/ /*auto mode off*/
|
halrf_wreg(rf, 0xc004, BIT(0), 0x0);
|
halrf_wreg(rf, 0xc024, BIT(0), 0x0);
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c);
|
/*step 15*/
|
halrf_wreg(rf, 0xc0d8, BIT(16), 0x0);
|
/*step 16*/
|
halrf_wreg(rf, 0x12a0, BIT(15), 0x0);
|
halrf_wreg(rf, 0x12a0, 0x7000, 0x7);
|
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]after S0 DADCK\n");
|
// halrf_check_dadc_8852b(rf, RF_PATH_A);
|
|
/*backup here*/
|
halrf_dack_backup_s0_8852b(rf);
|
// halrf_dack_reload_8852b(rf, RF_PATH_A);
|
/*step 17*/
|
halrf_wreg(rf, 0x12b8, BIT(30), 0x0);
|
}
|
|
void halrf_dack_8852b_s1(struct rf_info *rf)
|
{
|
struct halrf_dack_info *dack = &rf->dack;
|
u32 c = 0;
|
|
/*step 1*/
|
halrf_wreg(rf, 0x32a0, BIT(15), 0x1);
|
halrf_wreg(rf, 0x32a0, 0x7000, 0x3);
|
/*step 2*/
|
halrf_wreg(rf, 0x32b8, BIT(30), 0x1);
|
halrf_wreg(rf, 0x030c, BIT(28), 0x1);
|
halrf_wreg(rf, 0x032c, 0x80000000, 0x0);
|
/*step 3*/
|
halrf_wreg(rf, 0xc1d8, BIT(16), 0x1);
|
/*step 4*/
|
halrf_wreg(rf, 0xc1dc, BIT(27) | BIT(26), 0x3);
|
/*step 5*/
|
halrf_wreg(rf, 0xc104, BIT(30), 0x0);
|
halrf_wreg(rf, 0xc124, BIT(30), 0x0);
|
/*step 6*/
|
halrf_wreg(rf, 0xc104, 0x3ff00000, 0x30);
|
// halrf_wreg(rf, 0xc024, 0x3ff00000, 0x30);
|
/*step 7*/
|
halrf_wreg(rf, 0xc104, BIT(31) | BIT(30), 0x0);
|
// halrf_wreg(rf, 0xc124, BIT(31) | BIT(30), 0x0);
|
/*step 8*/
|
halrf_wreg(rf, 0xc104, BIT(17), 0x1);
|
halrf_wreg(rf, 0xc124, BIT(17), 0x1);
|
halrf_wreg(rf, 0xc10c, BIT(2), 0x0);
|
halrf_wreg(rf, 0xc12c, BIT(2), 0x0);
|
/*step 9*/ /*auto mode*/
|
halrf_wreg(rf, 0xc104, BIT(0), 0x1);
|
halrf_wreg(rf, 0xc124, BIT(0), 0x1);
|
halrf_delay_us(rf, 1);
|
/*step 10*/
|
c = 0x0;
|
while((halrf_rreg(rf, 0xc140, BIT(31)) == 0) && (halrf_rreg(rf, 0xc164, BIT(31)) == 0)) {
|
c++;
|
halrf_delay_us(rf, 1);
|
if (c > 10000) {
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 MSBK timeout\n");
|
dack->msbk_timeout[1] = true;
|
break;
|
}
|
}
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c);
|
/*step 11*/
|
halrf_wreg(rf, 0xc1dc, BIT(27) | BIT(26), 0x0);
|
/*step 12*/
|
halrf_wreg(rf, 0xc10c, BIT(2), 0x1);
|
halrf_wreg(rf, 0xc12c, BIT(2), 0x1);
|
halrf_delay_us(rf, 1);
|
/*step 13*/
|
c = 0x0;
|
while(halrf_rreg(rf, 0xc15c, BIT(2)) == 0 && halrf_rreg(rf, 0xc180, BIT(2)) == 0) {
|
c++;
|
halrf_delay_us(rf, 1);
|
if (c > 10000) {
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 DADCK timeout\n");
|
dack->dadck_timeout[1] = true;
|
break;
|
}
|
}
|
/*step 14*/ /*auto mode off*/
|
halrf_wreg(rf, 0xc104, BIT(0), 0x0);
|
halrf_wreg(rf, 0xc124, BIT(0), 0x0);
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c);
|
/*step 15*/
|
halrf_wreg(rf, 0xc1d8, BIT(16), 0x0);
|
/*step 16*/
|
halrf_wreg(rf, 0x32a0, BIT(15), 0x0);
|
halrf_wreg(rf, 0x32a0, 0x7000, 0x7);
|
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]after S1 DADCK\n");
|
halrf_check_dadc_8852b(rf, RF_PATH_B);
|
/*backup here*/
|
halrf_dack_backup_s1_8852b(rf);
|
// halrf_dack_reload_8852b(rf, RF_PATH_B);
|
/*step 17*/
|
halrf_wreg(rf, 0x32b8, BIT(30), 0x0);
|
}
|
|
void halrf_dack_8852b(struct rf_info *rf)
|
{
|
halrf_dack_8852b_s0(rf);
|
halrf_dack_8852b_s1(rf);
|
}
|
|
void halrf_dack_dump_8852b(struct rf_info *rf)
|
{
|
struct halrf_dack_info *dack = &rf->dack;
|
u8 i;
|
u8 t;
|
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n",
|
dack->addck_d[0][0], dack->addck_d[0][1] );
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n",
|
dack->addck_d[1][0], dack->addck_d[1][1] );
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
|
dack->dadck_d[0][0], dack->dadck_d[0][1] );
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
|
dack->dadck_d[1][0], dack->dadck_d[1][1] );
|
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n",
|
dack->biask_d[0][0], dack->biask_d[0][1] );
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n",
|
dack->biask_d[1][0], dack->biask_d[1][1] );
|
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 MSBK ic:\n");
|
for (i = 0; i < 0x10; i++) {
|
t = dack->msbk_d[0][0][i];
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t);
|
}
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 MSBK qc:\n");
|
for (i = 0; i < 0x10; i++) {
|
t = dack->msbk_d[0][1][i];
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t);
|
}
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 MSBK ic:\n");
|
for (i = 0; i < 0x10; i++) {
|
t = dack->msbk_d[1][0][i];
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t);
|
}
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 MSBK qc:\n");
|
for (i = 0; i < 0x10; i++) {
|
t = dack->msbk_d[1][1][i];
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t);
|
}
|
}
|
|
void halrf_dac_cal_8852b(struct rf_info *rf, bool force)
|
{
|
struct halrf_dack_info *dack = &rf->dack;
|
u32 rf0_0, rf1_0;
|
u8 phy_map;
|
|
phy_map = (BIT(HW_PHY_0) << 4) | RF_AB;
|
#if 0
|
if (dack->dack_en) {
|
if (!force) {
|
halrf_dack_reload_8852a(rf);
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]reload dack value\n");
|
return;
|
}
|
} else {
|
dack->dack_en = true;
|
}
|
#endif
|
dack->dack_done = false;
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK 0x1\n");
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK start!!!\n");
|
rf0_0 = halrf_rrf(rf,RF_PATH_A, 0x0, MASKRF);
|
rf1_0 = halrf_rrf(rf,RF_PATH_B, 0x0, MASKRF);
|
#if 1
|
halrf_afe_init_8852b(rf);
|
halrf_drck_8852b(rf);
|
halrf_wrf(rf, RF_PATH_A, 0x5, BIT(0), 0x0);
|
halrf_wrf(rf, RF_PATH_B, 0x5, BIT(0), 0x0);
|
halrf_wrf(rf, RF_PATH_A, 0x0, MASKRF, 0x337e1);
|
halrf_wrf(rf, RF_PATH_B, 0x0, MASKRF, 0x337e1);
|
// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_START);
|
halrf_addck_8852b(rf);
|
// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_STOP);
|
halrf_addck_backup_8852b(rf);
|
halrf_addck_reload_8852b(rf);
|
// halrf_wrf(rf, RF_PATH_A, 0x0, MASKRF, 0x40001);
|
// halrf_wrf(rf, RF_PATH_B, 0x0, MASKRF, 0x40001);
|
halrf_wrf(rf, RF_PATH_A, 0x1, MASKRF, 0x0);
|
halrf_wrf(rf, RF_PATH_B, 0x1, MASKRF, 0x0);
|
// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_START);
|
halrf_dack_8852b(rf);
|
// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_STOP);
|
halrf_dack_dump_8852b(rf);
|
dack->dack_done = true;
|
halrf_wrf(rf, RF_PATH_A, 0x0, MASKRF, rf0_0);
|
halrf_wrf(rf, RF_PATH_B, 0x0, MASKRF, rf1_0);
|
halrf_wrf(rf, RF_PATH_A, 0x5, BIT(0), 0x1);
|
halrf_wrf(rf, RF_PATH_B, 0x5, BIT(0), 0x1);
|
#endif
|
dack->dack_cnt++;
|
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK finish!!!\n");
|
}
|
#endif
|
