/** @file */
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/******************************************************************************
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*
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* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#ifndef __HALMAC_PCIE_REG_H__
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#define __HALMAC_PCIE_REG_H__
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/* PCIE PHY register */
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#define RAC_CTRL_PPR 0x00
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#define RAC_ANA10 0x10
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#define RAC_ANA19 0x19
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#define RAC_REG_REV2 0x1B
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#define BAC_CMU_EN_DLY_SH 12
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#define BAC_CMU_EN_DLY_MSK 0xF
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#define RAC_REG_FLD_0 0x1D
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#define BAC_AUTOK_N_SH 2
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#define BAC_AUTOK_N_MSK 0x3
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#define RAC_ANA1F 0x1F
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#define RAC_SET_PPR 0x20
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#define RAC_TRG_PPR 0x21
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#define RAC_ANA24 0x24
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#define RAC_ANA26 0x26
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#define RAC_CTRL_PPR_V1 0x30
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#define BAC_AUTOK_DIV_SH 14
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#define BAC_AUTOK_DIV_MSK 0x3
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#define BAC_AUTOK_EN BIT(13)
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#define BAC_AUTOK_ONCE_EN BIT(12)
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#define BAC_AUTOK_HW_TAR_SH 0
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#define BAC_AUTOK_HW_TAR_MSK 0xFFF
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#define RAC_SET_PPR_V1 0x31
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#define BAC_AUTOK_MGN_SH 12
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#define BAC_AUTOK_MGN_MSK 0xF
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#define BAC_AUTOK_TAR_SH 0
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#define BAC_AUTOK_TAR_MSK 0xFFF
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/* PCIE CFG register */
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#define PCIE_L1_STS 0x80
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#define PCIE_PHY_RATE 0x82
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#define PCIE_L1SS_CTRL 0x718
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#define PCIE_L1_CTRL 0x719
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#define PCIE_ACK_NFTS 0x70D
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#define PCIE_COM_CLK_NFTS 0x70E
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#define PCIE_FTS 0x80C
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#define PCIE_ASPM_CTRL 0x70F
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#define PCIE_CLK_CTRL 0x725
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#define CFG_RST_MSTATE 0xB48
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#define PCIE_L1SS_CAP 0x160
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#define PCIE_L1SS_SUP 0x164
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#define PCIE_L1SS_STS 0x168
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/* PCIE CFG bit */
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#define PCIE_BIT_STS_L0S BIT(0)
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#define PCIE_BIT_STS_L1 BIT(1)
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#define PCIE_BIT_WAKE BIT(2)
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#define PCIE_BIT_L1 BIT(3)
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#define PCIE_BIT_CLK BIT(4)
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#define PCIE_BIT_L0S BIT(7)
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#define PCIE_BIT_L1SS BIT(5)
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#define PCIE_BIT_L1SSSUP BIT(4)
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/* PCIE ASPM mask*/
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#define SHFT_L1DLY 3
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#define SHFT_L0SDLY 0
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#define PCIE_ASPMDLY_MASK 0x07
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#define PCIE_L1SS_MASK 0x0F
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/* PCIE Capability */
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#define PCIE_L1SS_ID 0x001E
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/* PCIE MAC register */
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#define LINK_CTRL2_REG_OFFSET 0xA0
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#define GEN2_CTRL_OFFSET 0x80C
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#define LINK_STATUS_REG_OFFSET 0x82
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#define PCIE_GEN1_SPEED 0x01
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#define PCIE_GEN2_SPEED 0x02
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#endif/* __HALMAC_PCIE_REG_H__ */
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