/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HAL_GENERAL_DEF_H_
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#define _HAL_GENERAL_DEF_H_
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#define RTW_MAC_TBTT_AGG_DEF 1
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enum rtw_chip_id {
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CHIP_WIFI6_8852A,
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CHIP_WIFI6_8834A,
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CHIP_WIFI6_8852B,
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CHIP_WIFI6_8852C,
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CHIP_WIFI6_MAX
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};
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enum rtw_efuse_info {
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/* MAC Part */
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EFUSE_INFO_MAC_ADDR,
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EFUSE_INFO_MAC_PID,
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EFUSE_INFO_MAC_DID,
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EFUSE_INFO_MAC_VID,
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EFUSE_INFO_MAC_SVID,
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EFUSE_INFO_MAC_SMID,
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EFUSE_INFO_MAC_MAX,
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/* BB Part */
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EFUSE_INFO_BB_ANTDIV,
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EFUSE_INFO_BB_MAX,
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/* RF Part */
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EFUSE_INFO_RF_PKG_TYPE,
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EFUSE_INFO_RF_PA,
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EFUSE_INFO_RF_VALID_PATH,
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EFUSE_INFO_RF_RFE,
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EFUSE_INFO_RF_TXPWR,
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EFUSE_INFO_RF_BOARD_OPTION,
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EFUSE_INFO_RF_CHAN_PLAN,
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EFUSE_INFO_RF_CHAN_PLAN_FORCE_HW,
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EFUSE_INFO_RF_COUNTRY,
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EFUSE_INFO_RF_THERMAL,
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EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1,
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EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2,
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EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3,
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EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4,
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EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5,
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EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6,
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EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1,
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EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2,
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EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3,
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EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4,
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EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13,
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EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14,
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EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1,
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EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2,
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EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3,
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EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4,
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EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5,
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EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6,
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EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1,
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EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2,
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EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3,
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EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4,
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EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13,
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EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14,
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EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_1,
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EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_2,
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EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_3,
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EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_4,
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EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_5,
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EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_6,
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EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_1,
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EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_2,
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EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_3,
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EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_4,
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EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_5,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_1,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_2,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_3,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_4,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_5,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_6,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_7,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_8,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_9,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_10,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_11,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_12,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_13,
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EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_14,
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EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_1,
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EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_2,
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EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_3,
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EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_4,
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EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_5,
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EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_6,
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EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_1,
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EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_2,
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EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_3,
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EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_4,
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EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_5,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_1,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_2,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_3,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_4,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_5,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_6,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_7,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_8,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_9,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_10,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_11,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_12,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_13,
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EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_14,
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EFUSE_INFO_RF_THERMAL_A,
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EFUSE_INFO_RF_THERMAL_B,
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EFUSE_INFO_RF_THERMAL_C,
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EFUSE_INFO_RF_THERMAL_D,
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EFUSE_INFO_RF_XTAL,
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/*RX Gain K*/
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EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK,
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EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD,
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EFUSE_INFO_RF_RX_GAIN_K_A_5GL,
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EFUSE_INFO_RF_RX_GAIN_K_A_5GM,
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EFUSE_INFO_RF_RX_GAIN_K_A_5GH,
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EFUSE_INFO_RF_MAX,
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/* BTCOEX Part */
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EFUSE_INFO_BTCOEX_COEX,
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EFUSE_INFO_BTCOEX_ANT_NUM,
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EFUSE_INFO_BTCOEX_ANT_PATH,
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EFUSE_INFO_BTCOEX_MAX,
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};
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enum rtw_cv {
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CAV,
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CBV,
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CCV,
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CDV,
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CEV,
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CFV,
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CGV,
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CTV,
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CMAXV,
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};
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enum rtw_fv {
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FTV,
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FUV,
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FSV,
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};
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enum rtw_dv_sel {
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DAV,
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DDV,
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};
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enum hal_pwr_by_rate_setting {
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PW_BY_RATE_ON = 0,
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PW_BY_RATE_ALL_SAME = 1
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};
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enum hal_pwr_limit_type {
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PWLMT_BY_EFUSE = 0,
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PWLMT_DISABLE = 1,
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PWBYRATE_AND_PWLMT = 2
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};
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enum rtw_mac_gfunc {
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RTW_MAC_GPIO_WL_PD,
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RTW_MAC_GPIO_BT_PD,
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RTW_MAC_GPIO_WL_EXTWOL,
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RTW_MAC_GPIO_BT_GPIO,
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RTW_MAC_GPIO_WL_SDIO_INT,
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RTW_MAC_GPIO_BT_SDIO_INT,
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RTW_MAC_GPIO_WL_FLASH,
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RTW_MAC_GPIO_BT_FLASH,
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RTW_MAC_GPIO_SIC,
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RTW_MAC_GPIO_LTE_UART,
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RTW_MAC_GPIO_LTE_3W,
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RTW_MAC_GPIO_WL_PTA,
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RTW_MAC_GPIO_BT_PTA,
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RTW_MAC_GPIO_MAILBOX,
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RTW_MAC_GPIO_WL_LED,
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RTW_MAC_GPIO_OSC,
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RTW_MAC_GPIO_XTAL_CLK,
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RTW_MAC_GPIO_EXT_XTAL_CLK,
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RTW_MAC_GPIO_DBG_GNT,
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RTW_MAC_GPIO_WL_RFE_CTRL,
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RTW_MAC_GPIO_BT_UART_RQB,
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RTW_MAC_GPIO_BT_WAKE_HOST,
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RTW_MAC_GPIO_HOST_WAKE_BT,
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RTW_MAC_GPIO_DBG,
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RTW_MAC_GPIO_WL_UART_TX,
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RTW_MAC_GPIO_WL_UART_RX,
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RTW_MAC_GPIO_WL_JTAG,
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RTW_MAC_GPIO_SW_IO,
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/* keep last */
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RTW_MAC_GPIO_LAST,
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RTW_MAC_GPIO_MAX = RTW_MAC_GPIO_LAST,
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RTW_MAC_GPIO_INVALID = RTW_MAC_GPIO_LAST,
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RTW_MAC_GPIO_DFLT = RTW_MAC_GPIO_LAST,
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};
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#ifdef CONFIG_FW_IO_OFLD_SUPPORT
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enum rtw_mac_src_cmd_ofld {
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RTW_MAC_BB_CMD_OFLD = 0,
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RTW_MAC_RF_CMD_OFLD,
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RTW_MAC_MAC_CMD_OFLD,
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RTW_MAC_OTHER_CMD_OFLD
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};
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enum rtw_mac_cmd_type_ofld {
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RTW_MAC_WRITE_OFLD = 0,
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RTW_MAC_COMPARE_OFLD,
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RTW_MAC_DELAY_OFLD
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};
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enum rtw_mac_rf_path {
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RTW_MAC_RF_PATH_A = 0, //Radio Path A
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RTW_MAC_RF_PATH_B, //Radio Path B
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RTW_MAC_RF_PATH_C, //Radio Path C
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RTW_MAC_RF_PATH_D, //Radio Path D
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};
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struct rtw_mac_cmd {
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enum rtw_mac_src_cmd_ofld src;
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enum rtw_mac_cmd_type_ofld type;
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u8 lc;
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enum rtw_mac_rf_path rf_path;
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u16 offset;
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u16 id;
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u32 value;
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u32 mask;
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};
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enum rtw_fw_ofld_cap {
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FW_CAP_IO_OFLD = BIT(0),
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};
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#endif
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enum wl_func {
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EFUSE_WL_FUNC_NONE = 0,
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EFUSE_WL_FUNC_DRAGON = 0xe,
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EFUSE_WL_FUNC_GENERAL = 0xf
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};
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enum hw_stype{
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EFUSE_HW_STYPE_NONE = 0x0,
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EFUSE_HW_STYPE_GENERAL = 0xf
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};
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struct rtw_hal_mac_ax_cctl_info {
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/* dword 0 */
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u32 datarate:9;
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u32 force_txop:1;
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u32 data_bw:2;
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u32 data_gi_ltf:3;
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u32 darf_tc_index:1;
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u32 arfr_ctrl:4;
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u32 acq_rpt_en:1;
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u32 mgq_rpt_en:1;
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u32 ulq_rpt_en:1;
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u32 twtq_rpt_en:1;
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u32 rsvd0:1;
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u32 disrtsfb:1;
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u32 disdatafb:1;
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u32 tryrate:1;
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u32 ampdu_density:4;
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/* dword 1 */
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u32 data_rty_lowest_rate:9;
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u32 ampdu_time_sel:1;
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u32 ampdu_len_sel:1;
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u32 rts_txcnt_lmt_sel:1;
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u32 rts_txcnt_lmt:4;
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u32 rtsrate:9;
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u32 rsvd1:2;
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u32 vcs_stbc:1;
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u32 rts_rty_lowest_rate:4;
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/* dword 2 */
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u32 data_tx_cnt_lmt:6;
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u32 data_txcnt_lmt_sel:1;
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u32 max_agg_num_sel:1;
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u32 rts_en:1;
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u32 cts2self_en:1;
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u32 cca_rts:2;
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u32 hw_rts_en:1;
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u32 rts_drop_data_mode:2;
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u32 rsvd2:1;
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u32 ampdu_max_len:11;
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u32 ul_mu_dis:1;
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u32 ampdu_max_time:4;
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/* dword 3 */
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u32 max_agg_num:8;
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u32 ba_bmap:2;
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u32 rsvd3:6;
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u32 vo_lftime_sel:3;
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u32 vi_lftime_sel:3;
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u32 be_lftime_sel:3;
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u32 bk_lftime_sel:3;
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u32 sectype:4;
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/* dword 4 */
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u32 multi_port_id:3;
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u32 bmc:1;
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u32 mbssid:4;
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u32 navusehdr:1;
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u32 txpwr_mode:3;
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u32 data_dcm:1;
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u32 data_er:1;
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u32 data_ldpc:1;
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u32 data_stbc:1;
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u32 a_ctrl_bqr:1;
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u32 a_ctrl_uph:1;
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u32 a_ctrl_bsr:1;
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u32 a_ctrl_cas:1;
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u32 data_bw_er:1;
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u32 lsig_txop_en:1;
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u32 rsvd4:5;
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u32 ctrl_cnt_vld:1;
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u32 ctrl_cnt:4;
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/* dword 5 */
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u32 resp_ref_rate:9;
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u32 rsvd5:3;
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u32 all_ack_support:1;
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u32 bsr_queue_size_format:1;
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u32 rsvd6:1;
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u32 rsvd7:1;
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u32 ntx_path_en:4;
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u32 path_map_a:2;
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u32 path_map_b:2;
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u32 path_map_c:2;
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u32 path_map_d:2;
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u32 antsel_a:1;
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u32 antsel_b:1;
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u32 antsel_c:1;
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u32 antsel_d:1;
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/* dword 6 */
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u32 addr_cam_index:8;
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u32 paid:9;
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u32 uldl:1;
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u32 doppler_ctrl:2;
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u32 nominal_pkt_padding:2;
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u32 nominal_pkt_padding40:2;
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u32 txpwr_tolerence:4;
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u32 rsvd9:2;
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u32 nominal_pkt_padding80:2;
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/* dword 7 */
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u32 nc:3;
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u32 nr:3;
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u32 ng:2;
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u32 cb:2;
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u32 cs:2;
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u32 csi_txbf_en:1;
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u32 csi_stbc_en:1;
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u32 csi_ldpc_en:1;
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u32 csi_para_en:1;
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u32 csi_fix_rate:9;
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u32 csi_gi_ltf:3;
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u32 nominal_pkt_padding160:2;
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u32 csi_bw:2;
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};
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#endif /* _HAL_GENERAL_DEF_H_*/
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