#ifndef __INC_BTC_FW_DEF_H__
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#define __INC_BTC_FW_DEF_H__
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#pragma pack(push)
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#pragma pack(1)
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/*
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* shared FW Definition
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*/
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#define CXMREG_MAX 30
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#define FCXDEF_STEP 50 /* MUST fw_step size*/
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#define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
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enum btc_bt_rfk_counter {
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BTC_BCNT_RFK_REQ = 0,
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BTC_BCNT_RFK_GO = 1,
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BTC_BCNT_RFK_REJECT = 2,
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BTC_BCNT_RFK_FAIL = 3,
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BTC_BCNT_RFK_TIMEOUT = 4,
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BTC_BCNT_RFK_MAX
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};
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struct btc_rpt_ctrl_wl_fw_info {
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u32 cx_ver; /* match which driver's coex version */
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u32 cx_offload;
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u32 fw_ver;
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};
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struct btc_rpt_ctrl_info {
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u32 cnt; /* fw report counter */
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u32 en; /* report map */
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u32 para; /* not used */
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u32 cnt_c2h; /* fw send c2h counter */
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u32 cnt_h2c; /* fw recv h2c counter */
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u32 len_c2h; /* The total length of the last C2H */
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};
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struct btc_rpt_ctrl_a2dp_empty {
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u32 cnt_empty; /* a2dp empty count */
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u32 cnt_flowctrl; /* a2dp empty flow control counter */
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u32 cnt_tx;
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u32 cnt_ack;
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u32 cnt_nack;
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};
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struct btc_rpt_ctrl_bt_mailbox {
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u32 cnt_send_ok; /* fw send mailbox ok counter */
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u32 cnt_send_fail; /* fw send mailbox fail counter */
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u32 cnt_recv; /* fw recv mailbox counter */
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struct btc_rpt_ctrl_a2dp_empty a2dp;
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};
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#define FCX_BTCRPT_VER 2
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struct fbtc_rpt_ctrl {
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u8 fver;
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u8 rsvd;
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u16 rsvd1;
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struct btc_rpt_ctrl_info rpt_info;
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struct btc_rpt_ctrl_wl_fw_info wl_fw_info;
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struct btc_rpt_ctrl_bt_mailbox bt_mbx_info;
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u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX];
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};
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/*
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* ============== TDMA related ==============
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*/
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enum fbtc_tdma_template {
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CXTD_OFF = 0x0,
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CXTD_OFF_B2,
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CXTD_OFF_EXT,
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CXTD_FIX,
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CXTD_PFIX,
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CXTD_AUTO,
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CXTD_PAUTO,
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CXTD_AUTO2,
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CXTD_PAUTO2,
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CXTD_MAX
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};
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enum fbtc_tdma_type {
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CXTDMA_OFF = 0x0, /* tdma off */
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CXTDMA_FIX = 0x1, /* fixed slot */
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CXTDMA_AUTO = 0x2, /* auto slot */
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CXTDMA_AUTO2 = 0x3, /* extended auto slot */
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CXTDMA_MAX
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};
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enum fbtc_tdma_rx_flow_ctrl {
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CXFLC_OFF = 0x0, /* rx flow off */
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CXFLC_NULLP = 0x1, /* Null/Null-P */
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CXFLC_QOSNULL = 0x2, /* QOS Null/Null-P */
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CXFLC_CTS = 0x3, /* CTS to Self control */
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CXFLC_MAX
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};
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enum fbtc_tdma_wlan_tx_pause {
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CXTPS_OFF = 0x0, /* no wl tx pause*/
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CXTPS_ON = 0x1,
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CXTPS_MAX
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};
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/* define if ext-ctrl-slot allowed while TDMA off */
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enum fbtc_ext_ctrl_type {
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CXECTL_OFF = 0x0, /* tdma off */
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CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
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CXECTL_EXT = 0x2,
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CXECTL_MAX
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};
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union fbtc_rxflct {
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u8 val;
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u8 type: 3;
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u8 tgln_n: 5;
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};
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#define FCX_TDMA_VER 2
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struct fbtc_tdma {
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u8 type; /* refer to fbtc_tdma_type*/
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u8 rxflctrl; /* refer to fbtc_tdma_rx_flow_ctrl */
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u8 txflctrl; /* If WL stop Tx while enter BT-slot */
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u8 wtgle_n; /* wl slot toggle every toggle_n cycles */
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u8 leak_n; /* every leak_n cycle do leak detection */
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u8 ext_ctrl; /* refer to fbtc_ext_ctrl_type*/
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/* send rxflctrl to which role
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* enum role_type, default: 0 for single-role
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* if multi-role: [7:4] second-role, [3:0] fisrt-role
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*/
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u8 rxflctrl_role;
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u8 rsvd;
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};
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struct fbtc_1tdma {
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u8 fver;
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u8 rsvd;
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u16 rsvd1;
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struct fbtc_tdma tdma;
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};
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/*
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* ============== SLOT related ==============
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*/
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enum { /* slot */
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CXST_OFF = 0x0,
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CXST_B2W = 0x1,
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CXST_W1 = 0x2,
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CXST_W2 = 0x3,
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CXST_W2B = 0x4,
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CXST_B1 = 0x5,
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CXST_B2 = 0x6,
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CXST_B3 = 0x7,
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CXST_B4 = 0x8,
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CXST_LK = 0x9,
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CXST_BLK = 0xa,
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CXST_E2G = 0xb, /* for ext-control-slot 2G*/
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CXST_E5G = 0xc, /* for ext-control-slot 5G*/
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CXST_EBT = 0xd, /* for ext-control-slot BT*/
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CXST_ENULL = 0xe, /* for ext-control-slot Null*/
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CXST_WLK = 0xf, /* for WL link slot */
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CXST_W1FDD = 0x10,
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CXST_B1FDD = 0x11,
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CXST_MAX = 0x12 /* The max slot must be even*/
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};
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enum {
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CXEVNT_TDMA_ENTRY = 0x0,
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CXEVNT_WL_TMR,
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CXEVNT_B1_TMR,
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CXEVNT_B2_TMR,
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CXEVNT_B3_TMR,
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CXEVNT_B4_TMR,
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CXEVNT_W2B_TMR,
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CXEVNT_B2W_TMR,
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CXEVNT_BCN_EARLY,
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CXEVNT_A2DP_EMPTY,
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CXEVNT_LK_END,
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CXEVNT_RX_ISR,
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CXEVNT_RX_FC0,
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CXEVNT_RX_FC1,
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CXEVNT_BT_RELINK,
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CXEVNT_BT_RETRY,
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CXEVNT_E2G,
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CXEVNT_E5G,
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CXEVNT_EBT,
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CXEVNT_ENULL,
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CXEVNT_DRV_WLK,
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CXEVNT_BCN_OK,
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CXEVNT_BT_CHANGE,
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CXEVNT_EBT_EXTEND,
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CXEVNT_E2G_NULL1,
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CXEVNT_MAX
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};
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enum {
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CXBCN_ALL = 0x0,
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CXBCN_ALL_OK,
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CXBCN_BT_SLOT,
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CXBCN_BT_OK,
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CXBCN_MAX
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};
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/* Slot isolation Definition
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* Same definition as WL RX Definition
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*/
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enum {
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SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
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SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
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CXSTYPE_MAX
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};
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enum { /* TIME */
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CXT_BT = 0x0,
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CXT_WL = 0x1,
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CXT_MAX
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};
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enum { /* TIME-A2DP */
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CXT_FLCTRL_OFF = 0x0,
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CXT_FLCTRL_ON = 0x1,
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CXT_FLCTRL_MAX
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};
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enum { /* STEP TYPE */
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CXSTEP_NONE = 0x0,
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CXSTEP_EVNT = 0x1,
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CXSTEP_SLOT = 0x2,
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CXSTEP_MAX
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};
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enum {
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CXNULL_STATE_0 = 0,
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CXNULL_STATE_1 = 1,
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CXNULL_STATE_MAX = 2
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};
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enum {
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CXNULL_FAIL = 0,
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CXNULL_OK = 1,
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CXNULL_LATE = 2,
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CXNULL_RETRY = 3,
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CXNULL_TX = 4,
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CXNULL_MAX = 5
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};
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struct fbtc_set_drvinfo {
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u8 type;
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u8 len;
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u8 buf[1];
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};
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#define FCX_GPIODBG_VER 1
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#define BTC_DBG_MAX1 32
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struct fbtc_gpio_dbg {
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u8 fver;
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u8 rsvd;
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u16 rsvd2;
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u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
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u32 pre_state; /* the debug signal is 1 or 0 */
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u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position mapping */
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};
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#define FCX_MREG_VER 1
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struct fbtc_mreg_val {
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u8 fver;
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u8 reg_num;
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u16 rsvd;
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u32 mreg_val[CXMREG_MAX];
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};
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struct fbtc_mreg {
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u16 type;
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u16 bytes;
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u32 offset;
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};
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#define FCX_SLOT_VER 1
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struct fbtc_slot {
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u16 dur; /* slot duration */
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u32 cxtbl;
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u16 cxtype;
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};
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struct fbtc_1slot {
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u8 fver;
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u8 sid; /* slot id */
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struct fbtc_slot slot;
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};
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struct fbtc_slots {
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u8 fver;
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u8 tbl_num;
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u16 rsvd;
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u32 update_map;
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struct fbtc_slot slot[CXST_MAX];
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};
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#define FCX_STEP_VER 3
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struct fbtc_step {
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u8 type;
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u8 val;
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u16 difft;
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};
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struct fbtc_steps {
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u8 fver;
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u8 en;
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u16 rsvd;
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u32 cnt;
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struct fbtc_step step[FCXDEF_STEP];
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};
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#define FCX_CYSTA_VER 3
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struct fbtc_fdd_try_info {
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u16 cycles[CXT_FLCTRL_MAX];
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u16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
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u16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
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};
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struct fbtc_cycle_time_info {
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u16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
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u16 tmax[CXT_MAX]; /* max wl/bt cycle time */
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u16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
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};
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struct fbtc_a2dp_trx_stat {
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u8 empty_cnt;
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u8 retry_cnt;
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u8 tx_rate;
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u8 tx_cnt;
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u8 ack_cnt;
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u8 nack_cnt;
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u8 rsvd1;
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u8 rsvd2;
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};
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struct fbtc_cycle_a2dp_empty_info {
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u16 cnt; /* a2dp empty cnt */
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u16 cnt_timeout; /* a2dp empty timeout cnt*/
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u16 tavg; /* avg a2dp empty time */
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u16 tmax; /* max a2dp empty time */
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};
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struct fbtc_cycle_leak_info {
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u32 cnt_rximr; /* the rximr occur at leak slot */
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u16 tavg; /* avg leak-slot time */
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u16 tamx; /* max leak-slot time */
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};
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struct fbtc_cysta { /* statistics for cycles */
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u8 fver;
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u8 rsvd;
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u16 cycles; /* total cycle number */
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u16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /*record the wl/bt slot time, max_step = BTC_CYCLE_SLOT_MAX */
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struct fbtc_cycle_time_info cycle_time;
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struct fbtc_fdd_try_info fdd_try;
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struct fbtc_cycle_a2dp_empty_info a2dp_ept;
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struct fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
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struct fbtc_cycle_leak_info leak_slot;
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u32 slot_cnt[CXST_MAX]; /* slot count */
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u32 bcn_cnt[CXBCN_MAX];
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u32 collision_cnt; /* counter for event/timer occur at the same time */
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u32 skip_cnt;
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u32 except_cnt;
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u32 except_map;
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};
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#define FCX_NULLSTA_VER 2
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struct fbtc_cynullsta { /* cycle null statistics */
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u8 fver;
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u8 rsvd;
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u16 rsvd2;
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u32 tmax[CXNULL_STATE_MAX]; /* max_t for 0:null0/1:null1 */
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u32 tavg[CXNULL_STATE_MAX]; /* avg_t for 0:null0/1:null1 */
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u32 result[CXNULL_STATE_MAX][CXNULL_MAX]; /* result for null , 0:fail, 1:ok, 2:late, 3:retry */
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};
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#define FCX_BTVER_VER 1
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struct fbtc_btver {
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u8 fver;
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u8 rsvd;
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u16 rsvd2;
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u32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
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u32 fw_ver;
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u32 feature;
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};
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#define FCX_BTSCAN_VER 1
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struct fbtc_btscan {
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u8 fver;
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u8 rsvd;
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u16 rsvd2;
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u8 scan[6];
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};
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#define FCX_BTAFH_VER 1
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struct fbtc_btafh {
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u8 fver;
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u8 rsvd;
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u16 rsvd2;
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u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
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u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
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u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
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};
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#define FCX_BTDEVINFO_VER 1
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struct fbtc_btdevinfo {
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u8 fver;
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u8 rsvd;
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u16 vendor_id;
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u32 dev_name; /* only 24 bits valid */
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u32 flush_time;
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};
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/*
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* End of FW Definition
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*/
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#pragma pack(pop)
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#endif /* __INC_BTC_FW_DEF_H__ */
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