/******************************************************************************
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*
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* Copyright(c) 2016 - 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _RTL8852B_BTC_C_
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#include "../../hal_headers_le.h"
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#include "../hal_btc.h"
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#ifdef CONFIG_BTCOEX
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#ifdef CONFIG_RTL8852B
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#include "btc_8852b.h"
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/* WL rssi threshold in % (dbm = % - 110)
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* array size limit by BTC_WL_RSSI_THMAX
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* BT rssi threshold in % (dbm = % - 100)
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* array size limit by BTC_BT_RSSI_THMAX
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*/
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static const u8 btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
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static const u8 btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
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static struct btc_chip_ops btc_8852b_ops = {
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_8852b_rfe_type,
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_8852b_init_cfg,
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_8852b_wl_pri,
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_8852b_wl_tx_power,
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_8852b_wl_rx_gain,
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_8852b_wl_s1_standby,
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_8852b_wl_req_mac,
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_8852b_update_bt_cnt,
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_8852b_bt_rssi
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};
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/* Set WL/BT periodical moniter reg, Max size: CXMREG_MAX*/
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static struct fbtc_mreg btc_8852b_mon_reg[] = {
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{REG_MAC, 4, 0xda24},
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{REG_MAC, 4, 0xda28},
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{REG_MAC, 4, 0xda2c},
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{REG_MAC, 4, 0xda30},
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{REG_MAC, 4, 0xda4c},
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{REG_MAC, 4, 0xda10},
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{REG_MAC, 4, 0xda20},
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{REG_MAC, 4, 0xda34},
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{REG_MAC, 4, 0xcef4},
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{REG_MAC, 4, 0x8424},
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{REG_MAC, 4, 0xd200},
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{REG_MAC, 4, 0xd220},
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{REG_BB, 4, 0x980},
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/*{REG_RF, 2, 0x2},*/ /* for RF, bytes->path, 1:A, 2:B... */
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/*{REG_RF, 2, 0x18},*/
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/*{REG_BT_RF, 2, 0x9},*/
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/*{REG_BT_MODEM, 2, 0xa} */
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};
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/* wl_tx_power: 255->original, else-> bit7:signed bit, ex: 13:13dBm, 0x85:-5dBm
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* wl_rx_gain: 0->original, 1-> for Free-run, 2-> for BTG co-rx
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* bt_tx_power: decrease power, 0->original, 5 -> decreas 5dB.
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* bt_rx_gain: BT LNA constrain Level, 7->original
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*/
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struct btc_rf_trx_para btc_8852b_rf_ul[] = {
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{255, 0, 0, 7}, /* 0 -> original */
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{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
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{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
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{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
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{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
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{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
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{6, 1, 0, 7},
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{13, 1, 0, 7},
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{13, 1, 0, 7}
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};
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struct btc_rf_trx_para btc_8852b_rf_dl[] = {
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{255, 0, 0, 7}, /* 0 -> original */
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{255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
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{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
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{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
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{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
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{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
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{255, 1, 0, 7},
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{255, 1, 0, 7},
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{255, 1, 0, 7}
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};
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const struct btc_chip chip_8852b = {
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CHIP_WIFI6_8852B, /* chip id */
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0x0, /* chip para ver */
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0x6, /* desired bt_ver */
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0x06010000, /* desired halbtc ver */
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0x1, /* scoreboard version */
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0x1, /* mailbox version*/
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BTC_COEX_RTK_MODE, /* pta_mode */
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BTC_COEX_INNER, /* pta_direction */
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6, /* afh_guard_ch */
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btc_8852b_wl_rssi_thres, /* wl rssi threshold level */
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btc_8852b_bt_rssi_thres, /* bt rssi threshold level */
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(u8)2, /* rssi tolerance */
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&btc_8852b_ops, /* chip-dependent function */
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ARRAY_SIZE(btc_8852b_mon_reg),
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btc_8852b_mon_reg, /* wl moniter register */
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ARRAY_SIZE(btc_8852b_rf_ul),
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btc_8852b_rf_ul,
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ARRAY_SIZE(btc_8852b_rf_dl),
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btc_8852b_rf_dl
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};
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void _8852b_rfe_type(struct btc_t *btc)
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{
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struct rtw_phl_com_t *p = btc->phl;
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struct rtw_hal_com_t *h = btc->hal;
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struct btc_module *module = &btc->mdinfo;
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PHL_INFO("[BTC], %s !! \n", __FUNCTION__);
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module->rfe_type = p->dev_cap.rfe_type;/* get from final capability of device */
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module->kt_ver = h->cv;
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module->bt_solo = 0;
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module->switch_type = BTC_SWITCH_INTERNAL;
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#if BTC_NON_SHARED_ANT_FREERUN
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module->ant.num = 3;
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#else
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if (module->rfe_type > 0)
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module->ant.num = (module->rfe_type % 2? 2 : 3);
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else
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module->ant.num = 2;
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#endif
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module->ant.diversity = 0;
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module->ant.isolation = 10;
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if (module->ant.num == 3) {
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module->ant.type = BTC_ANT_DEDICATED;
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module->bt_pos = BTC_BT_ALONE;
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} else {
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module->ant.type = BTC_ANT_SHARED;
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module->bt_pos = BTC_BT_BTG;
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}
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}
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void _8852b_wl_tx_power(struct btc_t *btc, u32 level)
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{
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/*
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* =========== All-Time WL Tx power control ===========
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* (ex: all-time fix WL Tx 10dBm , don¡¦t care GNT _BT and GNT _LTE)
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* Turn off per-packet power control
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* 0xD220[1] = 0, 0xD220[2] = 0;
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*
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* disable using related power table
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* 0xd208[20] = 0, 0xd208[21] = 0, 0xd21c[17] = 0, 0xd20c[29] = 0;
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*
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* enable force tx power mode and value
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* 0xD200[9] = 1;
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* 0xD200[8:0] = 0x28; S(9,2): 1step= 0.25dB, i.e. 40*0.25 = 10 dBm
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* =======================================================
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*
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* =========== per-packet Tx power control ===========
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* (ex: GNT_BT = 1 -> 5dBm, GNT _BT = 0 -> 10dBm)
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* Turn on per-packet power control
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* 0xD220[1] = 1, 0xD220[2] = 0;
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* 0xD220[11:3] = 0x14; S(9,2): 1step = 0.25dB, i.e. 20*0.25 = 5 dBm
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*
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* disable using related power table
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* 0xd208[20] = 0, 0xd208[21] = 0, 0xd21c[17] = 0, 0xd20c[29] = 0;
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*
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* enable force tx power mode and value
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* 0xD200[9] = 1;
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* 0xD200[8:0] = 0x28; S(9,2), sign, 1 step = 0.25dB, i.e. 40*0.25 = 10 dBm
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* =========================================================================
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*
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* level define:
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* if level = 255 -> back to original (btc don't control)
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* else in dBm --> bit7->signed bit, ex: 0xa-> +10dBm, 0x85-> -5dBm
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* pwr_val define:
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bit15~0 --> All-time (GNT_BT = 0) Tx power control
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bit31~16 --> Per-Packet (GNT_BT = 1) Tx power control
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*/
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u32 pwr_val;
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if (level == BTC_WL_DEF_TX_PWR) { /* back to original */
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pwr_val = bMASKDW;
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} else { /* only apply "force tx power" */
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pwr_val = (level & 0x7f) << 2; /* to fit s(9,2) format */
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if (pwr_val > BTC_WL_DEF_TX_PWR)
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pwr_val = BTC_WL_DEF_TX_PWR;
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if (level & BIT(7)) /* negative value */
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pwr_val |= BIT(8); /* to fit s(9,2) format */
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pwr_val |= bMASKHW;
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}
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rtw_hal_rf_wl_tx_power_control(btc->hal, pwr_val);
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}
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void _8852b_set_wl_lna2(struct btc_t *btc, u8 level)
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{
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/* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
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* level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
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* To improve BT ACI in co-rx
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*/
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#if 0 /* RDC: disable this function for A-cut RxA TIA gain bug,
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* it should be enabled for B-cut if nug fixed */
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switch (level) {
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case 0: /* default */
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_write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x1000);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x33, bMASKRF, 0x3);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x17);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x33, bMASKRF, 0x2);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x15);
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_write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x0);
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break;
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case 1: /* Fix LNA2=5 */
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_write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x1000);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x33, bMASKRF, 0x3);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x5);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x33, bMASKRF, 0x2);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x15);
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_write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x0);
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break;
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}
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#endif
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}
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void _8852b_wl_rx_gain(struct btc_t *btc, u32 level)
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{
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/* wl bb setting for FDD -> rtw_hal_bb_ctrl_btc_preagc()
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* OP1db Back-off(no LNA6) + Fixed TIA corner + RX_BB Back-off +
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* DFIR Type 3
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*/
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switch (level) {
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case 0: /* original */
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rtw_hal_bb_ctrl_btc_preagc(btc->hal, false);
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/* _8852b_set_wl_lna2(btc, 0); */
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break;
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case 1: /* for FDD free-run */
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rtw_hal_bb_ctrl_btc_preagc(btc->hal, true);
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/* _8852b_set_wl_lna2(btc, 0); */
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break;
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case 2: /* for BTG Co-Rx*/
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rtw_hal_bb_ctrl_btc_preagc(btc->hal, false);
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/* _8852b_set_wl_lna2(btc, 1); */
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break;
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}
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}
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u8 _8852b_bt_rssi(struct btc_t *btc, u8 val)
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{
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val = (val <= 127? 100 : (val >= 156? val - 156 : 0));
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val = val + 6; /* compensate offset */
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if (val > 100)
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val = 100;
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return (val);
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}
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void _8852b_set_wl_trx_mask(struct btc_t *btc, u8 path, u8 group, u32 val)
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{
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_write_wl_rf_reg(btc, path, 0xef, bMASKRF, 0x20000);
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_write_wl_rf_reg(btc, path, 0x33, bMASKRF, group);
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_write_wl_rf_reg(btc, path, 0x3f, bMASKRF, val);
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_write_wl_rf_reg(btc, path, 0xef, bMASKRF, 0x0);
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}
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void _8852b_wl_s1_standby(struct btc_t *btc, u32 state)
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{
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_write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x80000);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x33, bMASKRF, 0x1);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x3e, bMASKRF, 0x31);
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/* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
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if (state == 1)
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_write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x00579);
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else
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_write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x00020);
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_write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x0);
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}
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void _8852b_wl_req_mac(struct btc_t *btc, u8 mac_id)
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{
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u32 val1;
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val1 = _read_cx_reg(btc, R_BTC_CFG);
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if (mac_id == HW_PHY_0)
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val1 = val1 & (~B_BTC_WL_SRC);
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else
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val1 = val1 | B_BTC_WL_SRC;
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_write_cx_reg(btc, R_BTC_CFG, val1);
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}
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void _8852b_update_bt_cnt(struct btc_t *btc)
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{
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struct btc_cx *cx = &btc->cx;
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u32 val, val1;
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val = _read_cx_reg(btc, R_BTC_BT_STAST_HIGH);
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cx->cnt_bt[BTC_BCNT_HIPRI_TX] = val & bMASKLW;
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cx->cnt_bt[BTC_BCNT_HIPRI_RX] = (val & bMASKHW) >> 16;
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val = _read_cx_reg(btc, R_BTC_BT_STAST_LOW);
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cx->cnt_bt[BTC_BCNT_LOPRI_TX] = val & bMASKLW;
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cx->cnt_bt[BTC_BCNT_LOPRI_RX] = (val & bMASKHW) >> 16;
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/* clock-gate off before reset counter*/
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val1 = _read_cx_reg(btc, R_BTC_CFG);
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_write_cx_reg(btc, R_BTC_CFG, val1 | B_BTC_DIS_BTC_CLK_G);
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val = _read_cx_reg(btc, R_BTC_CSR_MODE);
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_write_cx_reg(btc, R_BTC_CSR_MODE, val & (~B_BTC_BT_CNT_REST));
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_write_cx_reg(btc, R_BTC_CSR_MODE, val | B_BTC_BT_CNT_REST);
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_write_cx_reg(btc, R_BTC_CFG, val1 & (~B_BTC_DIS_BTC_CLK_G));
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}
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void _8852b_init_cfg(struct btc_t *btc)
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{
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struct rtw_hal_com_t *h = btc->hal;
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struct btc_module *module = &btc->mdinfo;
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u32 val = 0;
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PHL_INFO("[BTC], %s !! \n", __FUNCTION__);
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/* PTA init */
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rtw_hal_mac_coex_init(h, chip_8852b.pta_mode, chip_8852b.pta_direction);
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/* set WL Tx response = Hi-Pri */
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btc->chip->ops->wl_pri(btc, BTC_PRI_MASK_TX_RESP, true);
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/* set WL Tx beacon = Hi-Pri */
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btc->chip->ops->wl_pri(btc, BTC_PRI_MASK_BEACON, true);
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/* set rf gnt debug off*/
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_write_wl_rf_reg(btc, RF_PATH_A, 0x2, bMASKRF, 0x0);
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_write_wl_rf_reg(btc, RF_PATH_B, 0x2, bMASKRF, 0x0);
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/* set WL Tx thru in TRX mask table if GNT_WL=0 && BT_S1=ss group */
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if (module->ant.type == BTC_ANT_SHARED) {
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_8852b_set_wl_trx_mask(btc, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
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_8852b_set_wl_trx_mask(btc, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
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/* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
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_8852b_set_wl_trx_mask(btc, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
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} else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
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_8852b_set_wl_trx_mask(btc, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
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_8852b_set_wl_trx_mask(btc, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
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}
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/* set PTA break table */
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_write_cx_reg(btc, R_BTC_BREAK_TABLE, 0xf0ffffff);
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/* enable BT counter 0xda40[16,2] = 2b'11 */
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val = _read_cx_reg(btc, R_BTC_CSR_MODE);
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_write_cx_reg(btc, R_BTC_CSR_MODE, val | BIT16 | BIT2);
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}
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void _8852b_wl_pri (struct btc_t *btc, u8 map, bool state)
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{
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u32 reg = 0, bitmap = 0, val = 0;
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switch (map) {
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case BTC_PRI_MASK_TX_RESP:
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reg = R_BTC_BT_COEX_MSK_TABLE;
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bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
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break;
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case BTC_PRI_MASK_BEACON:
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reg = R_BTC_WL_PRI_MSK;
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bitmap = B_BTC_PTA_WL_PRI_MASK_BCNQ;
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break;
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case BTC_PRI_MASK_RX_CCK:
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reg = R_BTC_BT_COEX_MSK_TABLE;
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bitmap = B_BTC_PRI_MASK_RXCCK_V1;
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break;
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}
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val = _read_cx_reg(btc, reg);
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if (state)
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val = val | bitmap;
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else
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val = val & (~bitmap);
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_write_cx_reg(btc, reg, val);
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}
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#endif /* CONFIG_RTL8852B */
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#endif
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