/**
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******************************************************************************
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*
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* rwnx_cmds.h
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*
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* Copyright (C) RivieraWaves 2014-2019
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*
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******************************************************************************
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*/
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#ifndef _AIC_BSP_DRIVER_H
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#define _AIC_BSP_DRIVER_H
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#include <linux/spinlock.h>
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#include <linux/completion.h>
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#include <linux/module.h>
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#include "aic_bsp_export.h"
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#define RWNX_80211_CMD_TIMEOUT_MS 3000//500//300
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#define RWNX_CMD_FLAG_NONBLOCK BIT(0)
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#define RWNX_CMD_FLAG_REQ_CFM BIT(1)
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#define RWNX_CMD_FLAG_WAIT_PUSH BIT(2)
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#define RWNX_CMD_FLAG_WAIT_ACK BIT(3)
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#define RWNX_CMD_FLAG_WAIT_CFM BIT(4)
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#define RWNX_CMD_FLAG_DONE BIT(5)
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/* ATM IPC design makes it possible to get the CFM before the ACK,
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* otherwise this could have simply been a state enum */
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#define RWNX_CMD_WAIT_COMPLETE(flags) \
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(!(flags & (RWNX_CMD_FLAG_WAIT_ACK | RWNX_CMD_FLAG_WAIT_CFM)))
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#define RWNX_CMD_MAX_QUEUED 8
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#define IPC_E2A_MSG_PARAM_SIZE 256
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#define RWNX_FN_ENTRY_STR ">>> %s()\n", __func__
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/* message levels */
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#define LOGERROR 0x0001
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#define LOGINFO 0x0002
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#define LOGTRACE 0x0004
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#define LOGDEBUG 0x0008
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#define LOGDATA 0x0010
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extern int aicwf_dbg_level_bsp;
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#define AICWF_LOG "AICWFDBG("
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#define AICWFDBG(level, args, arg...) \
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do { \
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if (aicwf_dbg_level_bsp & level) { \
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printk(AICWF_LOG#level")\t" args, ##arg); \
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} \
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} while (0)
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#define RWNX_DBG(fmt, ...) \
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do { \
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if (aicwf_dbg_level_bsp & LOGTRACE) { \
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printk(AICWF_LOG"LOGTRACE)\t"fmt , ##__VA_ARGS__); \
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} \
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} while (0)
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/// Message structure for MSGs from Emb to App
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struct ipc_e2a_msg {
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u16 id; ///< Message id.
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u16 dummy_dest_id;
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u16 dummy_src_id;
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u16 param_len; ///< Parameter embedded struct length.
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u32 pattern; ///< Used to stamp a valid MSG buffer
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u32 param[IPC_E2A_MSG_PARAM_SIZE]; ///< Parameter embedded struct. Must be word-aligned.
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};
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typedef u16 lmac_msg_id_t;
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typedef u16 lmac_task_id_t;
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struct lmac_msg {
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lmac_msg_id_t id; ///< Message id.
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lmac_task_id_t dest_id; ///< Destination kernel identifier.
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lmac_task_id_t src_id; ///< Source kernel identifier.
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u16 param_len; ///< Parameter embedded struct length.
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u32 param[]; ///< Parameter embedded struct. Must be word-aligned.
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};
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#define rwnx_cmd_e2amsg ipc_e2a_msg
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#define rwnx_cmd_a2emsg lmac_msg
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#define RWNX_CMD_A2EMSG_LEN(m) (sizeof(struct lmac_msg) + m->param_len)
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#define RWNX_CMD_E2AMSG_LEN_MAX (IPC_E2A_MSG_PARAM_SIZE * 4)
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static inline void put_u16(u8 *buf, u16 data)
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{
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buf[0] = (u8)(data&0x00ff);
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buf[1] = (u8)((data >> 8)&0x00ff);
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}
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enum rwnx_cmd_mgr_state {
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RWNX_CMD_MGR_STATE_DEINIT,
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RWNX_CMD_MGR_STATE_INITED,
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RWNX_CMD_MGR_STATE_CRASHED,
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};
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struct rwnx_cmd {
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struct list_head list;
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lmac_msg_id_t id;
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lmac_msg_id_t reqid;
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struct rwnx_cmd_a2emsg *a2e_msg;
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char *e2a_msg;
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u32 tkn;
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u16 flags;
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struct completion complete;
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u32 result;
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};
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struct aic_sdio_dev;
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struct rwnx_cmd;
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typedef int (*msg_cb_fct)(struct rwnx_cmd *cmd, struct rwnx_cmd_e2amsg *msg);
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struct rwnx_cmd_mgr {
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enum rwnx_cmd_mgr_state state;
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spinlock_t lock;
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u32 next_tkn;
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u32 queue_sz;
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u32 max_queue_sz;
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spinlock_t cb_lock;
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void *sdiodev;
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struct list_head cmds;
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int (*queue)(struct rwnx_cmd_mgr *, struct rwnx_cmd *);
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int (*llind)(struct rwnx_cmd_mgr *, struct rwnx_cmd *);
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int (*msgind)(struct rwnx_cmd_mgr *, struct rwnx_cmd_e2amsg *, msg_cb_fct);
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void (*print)(struct rwnx_cmd_mgr *);
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void (*drain)(struct rwnx_cmd_mgr *);
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struct work_struct cmdWork;
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struct workqueue_struct *cmd_wq;
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};
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void rwnx_cmd_mgr_init(struct rwnx_cmd_mgr *cmd_mgr);
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void rwnx_cmd_mgr_deinit(struct rwnx_cmd_mgr *cmd_mgr);
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int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd);
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void rwnx_set_cmd_tx(void *dev, struct lmac_msg *msg, uint len);
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enum {
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TASK_NONE = (u8) -1,
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// MAC Management task.
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TASK_MM = 0,
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// DEBUG task
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TASK_DBG,
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/// SCAN task
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TASK_SCAN,
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/// TDLS task
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TASK_TDLS,
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/// SCANU task
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TASK_SCANU,
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/// ME task
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TASK_ME,
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/// SM task
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TASK_SM,
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/// APM task
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TASK_APM,
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/// BAM task
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TASK_BAM,
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/// MESH task
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TASK_MESH,
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/// RXU task
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TASK_RXU,
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// This is used to define the last task that is running on the EMB processor
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TASK_LAST_EMB = TASK_RXU,
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// nX API task
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TASK_API,
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TASK_MAX,
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};
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#define LMAC_FIRST_MSG(task) ((lmac_msg_id_t)((task) << 10))
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#define DRV_TASK_ID 100
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#define MSG_I(msg) ((msg) & ((1<<10)-1))
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#define MSG_T(msg) ((lmac_task_id_t)((msg) >> 10))
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enum dbg_msg_tag {
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/// Memory read request
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DBG_MEM_READ_REQ = LMAC_FIRST_MSG(TASK_DBG),
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/// Memory read confirm
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DBG_MEM_READ_CFM,
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/// Memory write request
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DBG_MEM_WRITE_REQ,
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/// Memory write confirm
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DBG_MEM_WRITE_CFM,
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/// Module filter request
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DBG_SET_MOD_FILTER_REQ,
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/// Module filter confirm
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DBG_SET_MOD_FILTER_CFM,
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/// Severity filter request
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DBG_SET_SEV_FILTER_REQ,
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/// Severity filter confirm
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DBG_SET_SEV_FILTER_CFM,
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/// LMAC/MAC HW fatal error indication
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DBG_ERROR_IND,
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/// Request to get system statistics
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DBG_GET_SYS_STAT_REQ,
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/// COnfirmation of system statistics
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DBG_GET_SYS_STAT_CFM,
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/// Memory block write request
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DBG_MEM_BLOCK_WRITE_REQ,
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/// Memory block write confirm
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DBG_MEM_BLOCK_WRITE_CFM,
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/// Start app request
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DBG_START_APP_REQ,
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/// Start app confirm
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DBG_START_APP_CFM,
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/// Start npc request
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DBG_START_NPC_REQ,
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/// Start npc confirm
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DBG_START_NPC_CFM,
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/// Memory mask write request
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DBG_MEM_MASK_WRITE_REQ,
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/// Memory mask write confirm
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DBG_MEM_MASK_WRITE_CFM,
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DBG_RFTEST_CMD_REQ,
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DBG_RFTEST_CMD_CFM,
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DBG_BINDING_REQ,
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DBG_BINDING_CFM,
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DBG_BINDING_IND,
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DBG_CUSTOM_MSG_REQ,
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DBG_CUSTOM_MSG_CFM,
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DBG_CUSTOM_MSG_IND,
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DBG_GPIO_WRITE_REQ,
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DBG_GPIO_WRITE_CFM,
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/// Max number of Debug messages
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DBG_MAX,
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};
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#if !defined(CONFIG_M2D_OTA_LZMA_SUPPORT)
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#define FW_M2D_OTA_NAME "m2d_ota.bin"
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#else
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#define FW_M2D_OTA_NAME "m2d_ota_lzma.bin"
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#endif
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enum {
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HOST_START_APP_AUTO = 1,
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HOST_START_APP_CUSTOM,
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HOST_START_APP_FNCALL = 4,
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HOST_START_APP_DUMMY = 5,
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};
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struct dbg_mem_block_write_req {
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u32 memaddr;
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u32 memsize;
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u32 memdata[1024 / sizeof(u32)];
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};
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/// Structure containing the parameters of the @ref DBG_MEM_BLOCK_WRITE_CFM message.
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struct dbg_mem_block_write_cfm {
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u32 wstatus;
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};
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/// Structure containing the parameters of the @ref DBG_MEM_WRITE_REQ message.
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struct dbg_mem_write_req {
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u32 memaddr;
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u32 memdata;
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};
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/// Structure containing the parameters of the @ref DBG_MEM_WRITE_CFM message.
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struct dbg_mem_write_cfm {
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u32 memaddr;
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u32 memdata;
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};
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/// Structure containing the parameters of the @ref DBG_MEM_READ_REQ message.
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struct dbg_mem_read_req {
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u32 memaddr;
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};
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/// Structure containing the parameters of the @ref DBG_MEM_READ_CFM message.
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struct dbg_mem_read_cfm {
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u32 memaddr;
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u32 memdata;
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};
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/// Structure containing the parameters of the @ref DBG_MEM_MASK_WRITE_REQ message.
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struct dbg_mem_mask_write_req {
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u32 memaddr;
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u32 memmask;
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u32 memdata;
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};
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/// Structure containing the parameters of the @ref DBG_MEM_MASK_WRITE_CFM message.
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struct dbg_mem_mask_write_cfm {
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u32 memaddr;
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u32 memdata;
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};
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/// Structure containing the parameters of the @ref DBG_START_APP_REQ message.
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struct dbg_start_app_req {
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u32 bootaddr;
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u32 boottype;
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};
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/// Structure containing the parameters of the @ref DBG_START_APP_CFM message.
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struct dbg_start_app_cfm {
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u32 bootstatus;
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};
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int aicwf_plat_patch_load_8800dc(struct aic_sdio_dev *sdiodev);
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int aicwf_plat_rftest_load_8800dc(struct aic_sdio_dev *sdiodev);
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#ifdef CONFIG_DPD
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int aicwf_plat_calib_load_8800dc(struct aic_sdio_dev *sdiodev);
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#endif
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int rwnx_load_firmware(u32 **fw_buf, const char *name, struct device *device);
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int aicwf_patch_table_load(struct aic_sdio_dev *rwnx_hw, char *filename);
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int rwnx_send_dbg_mem_read_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
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struct dbg_mem_read_cfm *cfm);
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int rwnx_send_dbg_mem_block_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
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u32 mem_size, u32 *mem_data);
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int rwnx_send_dbg_mem_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr, u32 mem_data);
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int rwnx_send_dbg_mem_mask_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
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u32 mem_mask, u32 mem_data);
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int rwnx_send_dbg_start_app_req(struct aic_sdio_dev *sdiodev, u32 boot_addr, u32 boot_type, struct dbg_start_app_cfm *start_app_cfm);
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int rwnx_plat_bin_fw_upload_android(struct aic_sdio_dev *sdiodev, u32 fw_addr, const char *filename);
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void rwnx_rx_handle_msg(struct aic_sdio_dev *sdiodev, struct ipc_e2a_msg *msg);
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int aicbsp_platform_init(struct aic_sdio_dev *sdiodev);
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void aicbsp_platform_deinit(struct aic_sdio_dev *sdiodev);
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int aicbsp_driver_fw_init(struct aic_sdio_dev *sdiodev);
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#ifdef CONFIG_DPD
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int is_file_exist(char* name);
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#endif
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int aicbsp_resv_mem_init(void);
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int aicbsp_resv_mem_deinit(void);
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#define AICBSP_FW_PATH CONFIG_AIC_FW_PATH
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#define AICBSP_FW_PATH_MAX 200
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#define RAM_FMAC_FW_ADDR 0x00120000
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#define FW_RAM_ADID_BASE_ADDR 0x00161928
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#define FW_RAM_ADID_BASE_ADDR_U03 0x00161928
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#define FW_RAM_PATCH_BASE_ADDR 0x00100000
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#define RAM_8800DC_U01_ADID_ADDR 0x00101788
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#define RAM_8800DC_U02_ADID_ADDR 0x001017d8
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#define RAM_8800DC_FW_PATCH_ADDR 0x00184000
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#define FW_RESET_START_ADDR 0x40500128
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#define FW_RESET_START_VAL 0x40
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#define FW_ADID_FLAG_ADDR 0x40500150
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#define FW_ADID_FLAG_VAL 0x01
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#define FW_RAM_ADID_BASE_ADDR_8800D80 0x002017E0
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#define FW_RAM_PATCH_BASE_ADDR_8800D80 0x0020B2B0
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#define FW_RAM_ADID_BASE_ADDR_8800D80_U02 0x00201940
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#define FW_RAM_PATCH_BASE_ADDR_8800D80_U02 0x0020b43c
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#define AICBT_PT_TAG "AICBT_PT_TAG"
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/*****************************************************************************
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* Addresses within RWNX_ADDR_CPU
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*****************************************************************************/
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#define RAM_LMAC_FW_ADDR 0x00150000
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#define ROM_FMAC_FW_ADDR 0x00010000
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#define ROM_FMAC_PATCH_ADDR 0x00180000
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#define RWNX_MAC_CALIB_BASE_NAME_8800DC "fmacfw_calib_8800dc"
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#define RWNX_MAC_CALIB_NAME_8800DC_U02 RWNX_MAC_CALIB_BASE_NAME_8800DC"_u02.bin"
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#define RWNX_MAC_CALIB_NAME_8800DC_H_U02 RWNX_MAC_CALIB_BASE_NAME_8800DC"_h_u02.bin"
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#ifdef CONFIG_DPD
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#define ROM_FMAC_CALIB_ADDR 0x00130000
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#ifndef CONFIG_FORCE_DPD_CALIB
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#define FW_DPDRESULT_NAME_8800DC "aic_dpdresult_lite_8800dc.bin"
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#endif
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#endif
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#define RWNX_MAC_FW_RF_BASE_NAME_8800DC "lmacfw_rf_8800dc.bin"
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#ifdef CONFIG_FOR_IPCOM
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#define RWNX_MAC_PATCH_BASE_NAME_8800DC "fmacfw_patch_8800dc_ipc"
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#define RWNX_MAC_PATCH_NAME2_8800DC RWNX_MAC_PATCH_BASE_NAME_8800DC".bin"
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#else
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#define RWNX_MAC_PATCH_BASE_NAME_8800DC "fmacfw_patch_8800dc"
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#define RWNX_MAC_PATCH_NAME2_8800DC RWNX_MAC_PATCH_BASE_NAME_8800DC".bin"
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#define RWNX_MAC_PATCH_NAME2_8800DC_U02 RWNX_MAC_PATCH_BASE_NAME_8800DC"_u02.bin"
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#define RWNX_MAC_PATCH_NAME2_8800DC_H_U02 RWNX_MAC_PATCH_BASE_NAME_8800DC"_h_u02.bin"
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#endif
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#define RWNX_MAC_PATCH_TABLE_NAME_8800DC "fmacfw_patch_tbl_8800dc"
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#define RWNX_MAC_PATCH_TABLE_8800DC RWNX_MAC_PATCH_TABLE_NAME_8800DC ".bin"
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#define RWNX_MAC_PATCH_TABLE_8800DC_U02 RWNX_MAC_PATCH_TABLE_NAME_8800DC "_u02.bin"
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#define RWNX_MAC_PATCH_TABLE_8800DC_H_U02 RWNX_MAC_PATCH_TABLE_NAME_8800DC "_h_u02.bin"
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#define RWNX_MAC_RF_PATCH_BASE_NAME_8800DC "fmacfw_rf_patch_8800dc"
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#define RWNX_MAC_RF_PATCH_NAME_8800DC RWNX_MAC_RF_PATCH_BASE_NAME_8800DC".bin"
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#define FW_USERCONFIG_NAME_8800DC "aic_userconfig_8800dc.txt"
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enum {
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FW_NORMAL_MODE = 0,
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FW_RFTEST_MODE = 1,
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FW_BLE_SCAN_WAKEUP_MODE = 2,
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FW_M2D_OTA_MODE = 3,
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FW_DPDCALIB_MODE = 4,
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FW_BLE_SCAN_AD_FILTER_MODE = 5,
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};
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enum aicbt_patch_table_type {
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AICBT_PT_INF = 0x00,
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AICBT_PT_TRAP = 0x1,
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AICBT_PT_B4,
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AICBT_PT_BTMODE,
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AICBT_PT_PWRON,
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AICBT_PT_AF,
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AICBT_PT_VER,
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};
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enum aicbt_btport_type {
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AICBT_BTPORT_NULL,
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AICBT_BTPORT_MB,
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AICBT_BTPORT_UART,
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};
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/* btmode
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* used for force bt mode,if not AICBSP_MODE_NULL
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* efuse valid and vendor_info will be invalid, even has beed set valid
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*/
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enum aicbt_btmode_type {
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AICBT_BTMODE_BT_ONLY_SW = 0x0, // bt only mode with switch
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AICBT_BTMODE_BT_WIFI_COMBO, // wifi/bt combo mode
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AICBT_BTMODE_BT_ONLY, // bt only mode without switch
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AICBT_BTMODE_BT_ONLY_TEST, // bt only test mode
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AICBT_BTMODE_BT_WIFI_COMBO_TEST, // wifi/bt combo test mode
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AICBT_BTMODE_BT_ONLY_COANT, // bt only mode with no external switch
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AICBT_MODE_NULL = 0xFF, // invalid value
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};
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/* uart_baud
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* used for config uart baud when btport set to uart,
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* otherwise meaningless
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*/
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enum aicbt_uart_baud_type {
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AICBT_UART_BAUD_115200 = 115200,
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AICBT_UART_BAUD_921600 = 921600,
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AICBT_UART_BAUD_1_5M = 1500000,
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AICBT_UART_BAUD_3_25M = 3250000,
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};
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enum aicbt_uart_flowctrl_type {
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AICBT_UART_FLOWCTRL_DISABLE = 0x0, // uart without flow ctrl
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AICBT_UART_FLOWCTRL_ENABLE, // uart with flow ctrl
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};
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enum aicbsp_cpmode_type {
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AICBSP_CPMODE_WORK,
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AICBSP_CPMODE_TEST,
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AICBSP_CPMODE_MAX,
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};
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enum chip_rev {
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CHIP_REV_U01 = 1,
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CHIP_REV_U02 = 3,
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CHIP_REV_U03 = 7,
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CHIP_REV_U04 = 7,
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};
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#define AIC_M2D_OTA_INFO_ADDR 0x88000020
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#define AIC_M2D_OTA_DATA_ADDR 0x88000040
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#if !defined(CONFIG_M2D_OTA_LZMA_SUPPORT)
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#define AIC_M2D_OTA_FLASH_ADDR 0x08004000
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#define AIC_M2D_OTA_CODE_START_ADDR (AIC_M2D_OTA_FLASH_ADDR + 0x0188)
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#define AIC_M2D_OTA_VER_ADDR (AIC_M2D_OTA_FLASH_ADDR + 0x018C)
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#else
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#define AIC_M2D_OTA_FLASH_ADDR 0x08005000
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#define AIC_M2D_OTA_CODE_START_ADDR (AIC_M2D_OTA_FLASH_ADDR + 0x1188)
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#define AIC_M2D_OTA_VER_ADDR (AIC_M2D_OTA_FLASH_ADDR + 0x0010)
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#endif
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///aic bt tx pwr lvl :lsb->msb: first byte, min pwr lvl; second byte, max pwr lvl;
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///pwr lvl:20(min), 30 , 40 , 50 , 60(max)
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#define AICBT_TXPWR_LVL 0x00006020
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#define AICBT_TXPWR_LVL_8800dc 0x00006f2f
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#define AICBT_TXPWR_LVL_8800d80 0x00006f2f
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#define AICBSP_HWINFO_DEFAULT (-1)
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#define AICBSP_CPMODE_DEFAULT AICBSP_CPMODE_WORK
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#define AICBSP_FWLOG_EN_DEFAULT 0
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#define AICBT_BTMODE_DEFAULT_8800d80 AICBT_BTMODE_BT_ONLY_COANT
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#define AICBT_BTMODE_DEFAULT AICBT_BTMODE_BT_ONLY_SW
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#define AICBT_BTPORT_DEFAULT AICBT_BTPORT_UART
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#define AICBT_UART_BAUD_DEFAULT AICBT_UART_BAUD_1_5M
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#define AICBT_UART_FC_DEFAULT AICBT_UART_FLOWCTRL_ENABLE
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#define AICBT_LPM_ENABLE_DEFAULT 0
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#define AICBT_TXPWR_LVL_DEFAULT AICBT_TXPWR_LVL
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#define AICBT_TXPWR_LVL_DEFAULT_8800dc AICBT_TXPWR_LVL_8800dc
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#define AICBT_TXPWR_LVL_DEFAULT_8800d80 AICBT_TXPWR_LVL_8800d80
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|
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#define AIC_IRQ_WAKE_FLAG 0 // 0: rising edge, 1: falling edge
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#define FEATURE_SDIO_CLOCK 50000000 // 0: default, other: target clock rate
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#define FEATURE_SDIO_CLOCK_V3 150000000 // 0: default, other: target clock rate
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#define FEATURE_SDIO_PHASE 2 // 0: default, 2: 180°
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struct aicbt_patch_table {
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char *name;
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uint32_t type;
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uint32_t *data;
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uint32_t len;
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struct aicbt_patch_table *next;
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};
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struct aicbt_info_t {
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uint32_t btmode;
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uint32_t btport;
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uint32_t uart_baud;
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uint32_t uart_flowctrl;
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uint32_t lpm_enable;
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uint32_t txpwr_lvl;
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};
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struct aicbt_patch_info_t {
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uint32_t info_len;
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uint32_t adid_addrinf;
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uint32_t addr_adid;
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uint32_t patch_addrinf;
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uint32_t addr_patch;
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uint32_t reset_addr;
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uint32_t reset_val;
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uint32_t adid_flag_addr;
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uint32_t adid_flag;
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};
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struct aicbsp_firmware {
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const char *desc;
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const char *bt_adid;
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const char *bt_patch;
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const char *bt_table;
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const char *wl_fw;
|
};
|
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struct aicbsp_info_t {
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int hwinfo;
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int hwinfo_r;
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uint32_t cpmode;
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uint32_t chip_rev;
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bool fwlog_en;
|
uint8_t irqf;
|
};
|
|
extern struct aicbsp_info_t aicbsp_info;
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extern struct mutex aicbsp_power_lock;
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extern const struct aicbsp_firmware *aicbsp_firmware_list;
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extern const struct aicbsp_firmware fw_u02[];
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extern const struct aicbsp_firmware fw_u03[];
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extern const struct aicbsp_firmware fw_8800dc_u01[];
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extern const struct aicbsp_firmware fw_8800dc_u02[];
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extern const struct aicbsp_firmware fw_8800d80_u01[];
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extern const struct aicbsp_firmware fw_8800d80_u02[];
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#endif
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