#include "aic8800d80_compat.h"
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#include "aic_bsp_driver.h"
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extern struct aicbsp_info_t aicbsp_info;
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extern int adap_test;
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typedef u32 (*array2_tbl_t)[2];
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#define AIC_PATCH_MAGIG_NUM 0x48435450 // "PTCH"
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#define AIC_PATCH_MAGIG_NUM_2 0x50544348 // "HCTP"
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#define AIC_PATCH_BLOCK_MAX 4
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typedef struct {
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uint32_t magic_num;
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uint32_t pair_start;
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uint32_t magic_num_2;
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uint32_t pair_count;
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uint32_t block_dst[AIC_PATCH_BLOCK_MAX];
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uint32_t block_src[AIC_PATCH_BLOCK_MAX];
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uint32_t block_size[AIC_PATCH_BLOCK_MAX]; // word count
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} aic_patch_t;
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#define AIC_PATCH_OFST(mem) ((size_t) &((aic_patch_t *)0)->mem)
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#define AIC_PATCH_ADDR(mem) ((u32)(aic_patch_str_base + AIC_PATCH_OFST(mem)))
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u32 aicbsp_syscfg_tbl_8800d80[][2] = {
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};
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int aicbsp_system_config_8800d80(struct aic_sdio_dev *sdiodev)
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{
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int syscfg_num = sizeof(aicbsp_syscfg_tbl_8800d80) / sizeof(u32) / 2;
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int ret, cnt;
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for (cnt = 0; cnt < syscfg_num; cnt++) {
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ret = rwnx_send_dbg_mem_write_req(sdiodev, aicbsp_syscfg_tbl_8800d80[cnt][0], aicbsp_syscfg_tbl_8800d80[cnt][1]);
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if (ret) {
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printk("%x write fail: %d\n", aicbsp_syscfg_tbl_8800d80[cnt][0], ret);
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return ret;
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}
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}
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return 0;
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}
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u32 adaptivity_patch_tbl_8800d80[][2] = {
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{0x000C, 0x0000320A}, //linkloss_thd
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{0x009C, 0x00000000}, //ac_param_conf
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{0x0168, 0x00010000}, //tx_adaptivity_en
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};
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u32 patch_tbl_8800d80[][2] = {
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#ifdef USE_5G
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{0x00b4, 0xf3010001},
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#else
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{0x00b4, 0xf3010000},
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#endif
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#if defined(CONFIG_AMSDU_RX)
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{0x170, 0x0100000a}
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#endif
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#if AIC_IRQ_WAKE_FLAG
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{0x00000170, 0x0000010a}, //irqf
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#endif
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};
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#ifdef CONFIG_OOB
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// for 8800d40/d80 map data1 isr to gpiob1
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u32 gpio_cfg_tbl_8800d40d80[][2] = {
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{0x40504084, 0x00000006},
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{0x40500040, 0x00000000},
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{0x40100030, 0x00000001},
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{0x40241020, 0x00000001},
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{0x40240030, 0x00000004},
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{0x40240020, 0x03020700},
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};
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#endif
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int aicwifi_sys_config_8800d80(struct aic_sdio_dev *sdiodev)
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{
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#ifdef CONFIG_OOB
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int ret, cnt;
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int gpiocfg_num = sizeof(gpio_cfg_tbl_8800d40d80) / sizeof(u32) / 2;
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for (cnt = 0; cnt < gpiocfg_num; cnt++) {
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ret = rwnx_send_dbg_mem_write_req(sdiodev, gpio_cfg_tbl_8800d40d80[cnt][0], gpio_cfg_tbl_8800d40d80[cnt][1]);
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if (ret) {
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printk("%x write fail: %d\n", gpio_cfg_tbl_8800d40d80[cnt][0], ret);
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return ret;
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}
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}
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#endif
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return 0;
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}
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int aicwifi_patch_config_8800d80(struct aic_sdio_dev *sdiodev)
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{
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const u32 rd_patch_addr = RAM_FMAC_FW_ADDR + 0x0198;
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u32 aic_patch_addr;
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u32 config_base, aic_patch_str_base;
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uint32_t start_addr = 0x0016F800;
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u32 patch_addr = start_addr;
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u32 patch_cnt = sizeof(patch_tbl_8800d80)/sizeof(u32)/2;
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struct dbg_mem_read_cfm rd_patch_addr_cfm;
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int ret = 0;
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int cnt = 0;
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//adap test
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int adap_patch_cnt = 0;
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if (adap_test) {
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adap_patch_cnt = sizeof(adaptivity_patch_tbl_8800d80)/sizeof(u32)/2;
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}
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aic_patch_addr = rd_patch_addr + 8;
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ret = rwnx_send_dbg_mem_read_req(sdiodev, rd_patch_addr, &rd_patch_addr_cfm);
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if (ret) {
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printk("patch rd fail\n");
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return ret;
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}
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config_base = rd_patch_addr_cfm.memdata;
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ret = rwnx_send_dbg_mem_read_req(sdiodev, aic_patch_addr, &rd_patch_addr_cfm);
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if (ret) {
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printk("patch str rd fail\n");
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return ret;
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}
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aic_patch_str_base = rd_patch_addr_cfm.memdata;
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(magic_num), AIC_PATCH_MAGIG_NUM);
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if (ret) {
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printk("0x%x write fail\n", AIC_PATCH_ADDR(magic_num));
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return ret;
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(magic_num_2), AIC_PATCH_MAGIG_NUM_2);
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if (ret) {
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printk("0x%x write fail\n", AIC_PATCH_ADDR(magic_num_2));
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return ret;
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(pair_start), patch_addr);
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if (ret) {
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printk("0x%x write fail\n", AIC_PATCH_ADDR(pair_start));
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return ret;
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(pair_count), patch_cnt + adap_patch_cnt);
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if (ret) {
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printk("0x%x write fail\n", AIC_PATCH_ADDR(pair_count));
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return ret;
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}
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for (cnt = 0; cnt < patch_cnt; cnt++) {
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ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt, patch_tbl_8800d80[cnt][0]+config_base);
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if (ret) {
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printk("%x write fail\n", start_addr+8*cnt);
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return ret;
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt+4, patch_tbl_8800d80[cnt][1]);
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if (ret) {
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printk("%x write fail\n", start_addr+8*cnt+4);
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return ret;
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}
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}
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if (adap_test){
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int tmp_cnt = patch_cnt + adap_patch_cnt;
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for (cnt = patch_cnt; cnt < tmp_cnt; cnt++) {
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int tbl_idx = cnt - patch_cnt;
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ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt, adaptivity_patch_tbl_8800d80[tbl_idx][0]+config_base);
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if(ret) {
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printk("%x write fail\n", start_addr+8*cnt);
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return ret;
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt+4, adaptivity_patch_tbl_8800d80[tbl_idx][1]);
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if(ret) {
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printk("%x write fail\n", start_addr+8*cnt+4);
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return ret;
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}
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}
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[0]), 0);
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if (ret) {
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printk("block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[0]), ret);
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return ret;
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[1]), 0);
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if (ret) {
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printk("block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[1]), ret);
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return ret;
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[2]), 0);
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if (ret) {
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printk("block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[2]), ret);
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return ret;
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}
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ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[3]), 0);
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if (ret) {
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printk("block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[3]), ret);
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return ret;
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}
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return 0;
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}
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