/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC2_CFG_REGS_H_
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#define ASIC_REG_TPC2_CFG_REGS_H_
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/*
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*****************************************
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* TPC2_CFG (Prototype: TPC)
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*****************************************
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*/
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#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400
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#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404
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#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408
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#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C
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#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410
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#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414
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#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE86418
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#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE8641C
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#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86420
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#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE86424
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#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86428
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#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE8642C
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#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86430
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#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86434
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#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE86438
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#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE8643C
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#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86440
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#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86444
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#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE86448
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#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE8644C
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#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86450
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#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE86454
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#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86458
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#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE8645C
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#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86460
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#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86464
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#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE86468
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#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE8646C
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#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86470
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#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE86474
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#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE86478
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#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE8647C
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#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE86480
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#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE86484
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#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE86488
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#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE8648C
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#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE86490
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#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE86494
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#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE86498
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#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE8649C
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#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864A0
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#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864A4
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#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864A8
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#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864AC
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#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864B0
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#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864B4
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#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864B8
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#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864BC
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#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE864C0
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#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE864C4
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#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE864C8
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#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE864CC
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#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE864D0
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#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE864D4
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#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE864D8
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#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE864DC
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#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE864E0
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#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE864E4
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#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE864E8
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#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE864EC
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#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE864F0
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#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE864F4
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#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE864F8
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#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE864FC
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#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86500
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#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE86504
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#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86508
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#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE8650C
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#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86510
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#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86514
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#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE86518
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#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE8651C
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#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86520
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#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86524
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#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE86528
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#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE8652C
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#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86530
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#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE86534
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#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE86538
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#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE8653C
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#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE86540
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#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE86544
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#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE86548
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#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE8654C
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#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE86550
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#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE86554
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#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE86558
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#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE8655C
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#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE86560
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#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE86564
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#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE86568
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#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE8656C
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#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE86570
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#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE86574
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#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE86578
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#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE8657C
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#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86580
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#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE86584
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#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86588
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#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE8658C
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#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE86590
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#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86594
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#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86598
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#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE8659C
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#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE865A0
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#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE865A4
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#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE865A8
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#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE865AC
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#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE865B0
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#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE865B4
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#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE865B8
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#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE865BC
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#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE865C0
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#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE865C4
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#define mmTPC2_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE865C8
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#define mmTPC2_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE865CC
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#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE865D0
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#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE865D4
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#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE865D8
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#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE865DC
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#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE865E0
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#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE865E4
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#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE865E8
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#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE865EC
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#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE865F0
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#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE865F4
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#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE865F8
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#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE865FC
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#define mmTPC2_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE86600
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#define mmTPC2_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE86604
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#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE86608
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#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE8660C
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#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE86610
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#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE86614
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#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE86618
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#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE8661C
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#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE86620
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#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE86624
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#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE86628
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#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE8662C
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#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE86630
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#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE86634
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#define mmTPC2_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE86638
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#define mmTPC2_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE8663C
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#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE86640
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#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE86644
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#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE86648
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#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE8664C
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#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE86650
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#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE86654
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#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE86658
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#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE8665C
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#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE86660
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#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE86664
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#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE86668
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#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE8666C
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#define mmTPC2_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE86670
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#define mmTPC2_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE86674
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#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE86678
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#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE8667C
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#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE86680
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#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE86684
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#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE86688
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#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE8668C
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#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE86690
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#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE86694
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#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE86698
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#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE8669C
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#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE866A0
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#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE866A4
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#define mmTPC2_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE866A8
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#define mmTPC2_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE866AC
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#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE866B0
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#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE866B4
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#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE866B8
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#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE866BC
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#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE866C0
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#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE866C4
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#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE866C8
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#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE866CC
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#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE866D0
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#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE866D4
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#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE866D8
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#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE866DC
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#define mmTPC2_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE866E0
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#define mmTPC2_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE866E4
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#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE866E8
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#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE866EC
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#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE866F0
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#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE866F4
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#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE866F8
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#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE866FC
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#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE86700
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#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE86704
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#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE86708
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#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE8670C
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#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE86710
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#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE86714
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#define mmTPC2_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE86718
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#define mmTPC2_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE8671C
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#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE86720
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#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE86724
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#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE86728
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#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE8672C
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#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE86730
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#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE86734
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#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE86738
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#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE8673C
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#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE86740
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#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE86744
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#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE86748
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#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE8674C
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#define mmTPC2_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE86750
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#define mmTPC2_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE86754
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#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE86758
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#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE8675C
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#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE86760
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#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE86764
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#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE86768
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#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE8676C
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#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE86770
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#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE86774
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#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE86778
|
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#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE8677C
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#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86780
|
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#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE86784
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#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86788
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#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE8678C
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#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86790
|
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#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE86794
|
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#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86798
|
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#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE8679C
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#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE867A0
|
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#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE867A4
|
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#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE867A8
|
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#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE867AC
|
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#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE867B0
|
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#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE867B4
|
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#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE867B8
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#define mmTPC2_CFG_KERNEL_KERNEL_ID 0xE867BC
|
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#define mmTPC2_CFG_KERNEL_SRF_0 0xE867C0
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#define mmTPC2_CFG_KERNEL_SRF_1 0xE867C4
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#define mmTPC2_CFG_KERNEL_SRF_2 0xE867C8
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#define mmTPC2_CFG_KERNEL_SRF_3 0xE867CC
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#define mmTPC2_CFG_KERNEL_SRF_4 0xE867D0
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#define mmTPC2_CFG_KERNEL_SRF_5 0xE867D4
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#define mmTPC2_CFG_KERNEL_SRF_6 0xE867D8
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#define mmTPC2_CFG_KERNEL_SRF_7 0xE867DC
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#define mmTPC2_CFG_KERNEL_SRF_8 0xE867E0
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#define mmTPC2_CFG_KERNEL_SRF_9 0xE867E4
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#define mmTPC2_CFG_KERNEL_SRF_10 0xE867E8
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#define mmTPC2_CFG_KERNEL_SRF_11 0xE867EC
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#define mmTPC2_CFG_KERNEL_SRF_12 0xE867F0
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#define mmTPC2_CFG_KERNEL_SRF_13 0xE867F4
|
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#define mmTPC2_CFG_KERNEL_SRF_14 0xE867F8
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#define mmTPC2_CFG_KERNEL_SRF_15 0xE867FC
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#define mmTPC2_CFG_KERNEL_SRF_16 0xE86800
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#define mmTPC2_CFG_KERNEL_SRF_17 0xE86804
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#define mmTPC2_CFG_KERNEL_SRF_18 0xE86808
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#define mmTPC2_CFG_KERNEL_SRF_19 0xE8680C
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#define mmTPC2_CFG_KERNEL_SRF_20 0xE86810
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#define mmTPC2_CFG_KERNEL_SRF_21 0xE86814
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#define mmTPC2_CFG_KERNEL_SRF_22 0xE86818
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#define mmTPC2_CFG_KERNEL_SRF_23 0xE8681C
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#define mmTPC2_CFG_KERNEL_SRF_24 0xE86820
|
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#define mmTPC2_CFG_KERNEL_SRF_25 0xE86824
|
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#define mmTPC2_CFG_KERNEL_SRF_26 0xE86828
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#define mmTPC2_CFG_KERNEL_SRF_27 0xE8682C
|
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#define mmTPC2_CFG_KERNEL_SRF_28 0xE86830
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#define mmTPC2_CFG_KERNEL_SRF_29 0xE86834
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#define mmTPC2_CFG_KERNEL_SRF_30 0xE86838
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#define mmTPC2_CFG_KERNEL_SRF_31 0xE8683C
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#define mmTPC2_CFG_ROUND_CSR 0xE868FC
|
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#define mmTPC2_CFG_PROT 0xE86900
|
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#define mmTPC2_CFG_SEMAPHORE 0xE86908
|
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#define mmTPC2_CFG_VFLAGS 0xE8690C
|
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#define mmTPC2_CFG_SFLAGS 0xE86910
|
|
#define mmTPC2_CFG_LFSR_POLYNOM 0xE86918
|
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#define mmTPC2_CFG_STATUS 0xE8691C
|
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#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86920
|
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#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86924
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#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8692C
|
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#define mmTPC2_CFG_TPC_CMD 0xE86930
|
|
#define mmTPC2_CFG_TPC_EXECUTE 0xE86938
|
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#define mmTPC2_CFG_TPC_STALL 0xE8693C
|
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#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86940
|
|
#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86944
|
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#define mmTPC2_CFG_RD_RATE_LIMIT 0xE86948
|
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#define mmTPC2_CFG_WR_RATE_LIMIT 0xE86950
|
|
#define mmTPC2_CFG_MSS_CONFIG 0xE86954
|
|
#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86958
|
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#define mmTPC2_CFG_TPC_INTR_MASK 0xE8695C
|
|
#define mmTPC2_CFG_WQ_CREDITS 0xE86960
|
|
#define mmTPC2_CFG_ARUSER_LO 0xE86964
|
|
#define mmTPC2_CFG_ARUSER_HI 0xE86968
|
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#define mmTPC2_CFG_AWUSER_LO 0xE8696C
|
|
#define mmTPC2_CFG_AWUSER_HI 0xE86970
|
|
#define mmTPC2_CFG_OPCODE_EXEC 0xE86974
|
|
#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE86978
|
|
#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE8697C
|
|
#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE86980
|
|
#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE86984
|
|
#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE86988
|
|
#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE8698C
|
|
#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE86990
|
|
#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE86994
|
|
#define mmTPC2_CFG_TSB_CFG_MAX_SIZE 0xE86998
|
|
#define mmTPC2_CFG_TSB_CFG 0xE8699C
|
|
#define mmTPC2_CFG_DBGMEM_ADD 0xE869A0
|
|
#define mmTPC2_CFG_DBGMEM_DATA_WR 0xE869A4
|
|
#define mmTPC2_CFG_DBGMEM_DATA_RD 0xE869A8
|
|
#define mmTPC2_CFG_DBGMEM_CTRL 0xE869AC
|
|
#define mmTPC2_CFG_DBGMEM_RC 0xE869B0
|
|
#define mmTPC2_CFG_TSB_INFLIGHT_CNTR 0xE869B4
|
|
#define mmTPC2_CFG_WQ_INFLIGHT_CNTR 0xE869B8
|
|
#define mmTPC2_CFG_WQ_LBW_TOTAL_CNTR 0xE869BC
|
|
#define mmTPC2_CFG_WQ_HBW_TOTAL_CNTR 0xE869C0
|
|
#define mmTPC2_CFG_IRQ_OCCOUPY_CNTR 0xE869C4
|
|
#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE869D0
|
|
#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE869D4
|
|
#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE869D8
|
|
#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE869DC
|
|
#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE869E0
|
|
#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE869E4
|
|
#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE869E8
|
|
#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE869EC
|
|
#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE869F0
|
|
#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE869F4
|
|
#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE869F8
|
|
#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE869FC
|
|
#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00
|
|
#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04
|
|
#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08
|
|
#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C
|
|
#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10
|
|
#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14
|
|
#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A18
|
|
#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A1C
|
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#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A20
|
|
#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A24
|
|
#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A28
|
|
#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A2C
|
|
#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A30
|
|
#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A34
|
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#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A38
|
|
#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A3C
|
|
#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A40
|
|
#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A44
|
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#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A48
|
|
#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A4C
|
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#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A50
|
|
#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A54
|
|
#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A58
|
|
#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A5C
|
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#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A60
|
|
#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A64
|
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#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A68
|
|
#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A6C
|
|
#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A70
|
|
#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A74
|
|
#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86A78
|
|
#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86A7C
|
|
#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86A80
|
|
#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86A84
|
|
#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86A88
|
|
#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86A8C
|
|
#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86A90
|
|
#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86A94
|
|
#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86A98
|
|
#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86A9C
|
|
#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AA0
|
|
#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86AA4
|
|
#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AA8
|
|
#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AAC
|
|
#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AB0
|
|
#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AB4
|
|
#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AB8
|
|
#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86ABC
|
|
#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86AC0
|
|
#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86AC4
|
|
#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86AC8
|
|
#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86ACC
|
|
#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86AD0
|
|
#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86AD4
|
|
#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86AD8
|
|
#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86ADC
|
|
#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86AE0
|
|
#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86AE4
|
|
#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86AE8
|
|
#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86AEC
|
|
#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86AF0
|
|
#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86AF4
|
|
#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86AF8
|
|
#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86AFC
|
|
#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B00
|
|
#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B04
|
|
#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B08
|
|
#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B0C
|
|
#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B10
|
|
#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B14
|
|
#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B18
|
|
#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B1C
|
|
#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B20
|
|
#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B24
|
|
#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B28
|
|
#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B2C
|
|
#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B30
|
|
#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B34
|
|
#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86B38
|
|
#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86B3C
|
|
#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86B40
|
|
#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86B44
|
|
#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86B48
|
|
#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86B4C
|
|
#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86B50
|
|
#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86B54
|
|
#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86B58
|
|
#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86B5C
|
|
#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86B60
|
|
#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86B64
|
|
#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86B68
|
|
#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86B6C
|
|
#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86B70
|
|
#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86B74
|
|
#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86B78
|
|
#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86B7C
|
|
#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86B80
|
|
#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86B84
|
|
#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86B88
|
|
#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86B8C
|
|
#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86B90
|
|
#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86B94
|
|
#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86B98
|
|
#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86B9C
|
|
#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86BA0
|
|
#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86BA4
|
|
#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86BA8
|
|
#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86BAC
|
|
#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86BB0
|
|
#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86BB4
|
|
#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86BB8
|
|
#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86BBC
|
|
#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE86BC0
|
|
#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE86BC4
|
|
#define mmTPC2_CFG_QM_TENSOR_8_PADDING_VALUE 0xE86BC8
|
|
#define mmTPC2_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE86BCC
|
|
#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE86BD0
|
|
#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE86BD4
|
|
#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE86BD8
|
|
#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE86BDC
|
|
#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE86BE0
|
|
#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE86BE4
|
|
#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE86BE8
|
|
#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE86BEC
|
|
#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE86BF0
|
|
#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE86BF4
|
|
#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE86BF8
|
|
#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE86BFC
|
|
#define mmTPC2_CFG_QM_TENSOR_9_PADDING_VALUE 0xE86C00
|
|
#define mmTPC2_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE86C04
|
|
#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE86C08
|
|
#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE86C0C
|
|
#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE86C10
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#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE86C14
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#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE86C18
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#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE86C1C
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#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE86C20
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#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE86C24
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#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE86C28
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#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE86C2C
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#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE86C30
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#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE86C34
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#define mmTPC2_CFG_QM_TENSOR_10_PADDING_VALUE 0xE86C38
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#define mmTPC2_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE86C3C
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#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE86C40
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#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE86C44
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#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE86C48
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#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE86C4C
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#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE86C50
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#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE86C54
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#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE86C58
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#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE86C5C
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#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE86C60
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#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE86C64
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#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE86C68
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#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE86C6C
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#define mmTPC2_CFG_QM_TENSOR_11_PADDING_VALUE 0xE86C70
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#define mmTPC2_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE86C74
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#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE86C78
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#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE86C7C
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#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE86C80
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#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE86C84
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#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE86C88
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#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE86C8C
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#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE86C90
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#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE86C94
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#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE86C98
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#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE86C9C
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#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE86CA0
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#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE86CA4
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#define mmTPC2_CFG_QM_TENSOR_12_PADDING_VALUE 0xE86CA8
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#define mmTPC2_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE86CAC
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#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE86CB0
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#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE86CB4
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#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE86CB8
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#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE86CBC
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#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE86CC0
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#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE86CC4
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#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE86CC8
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#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE86CCC
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#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE86CD0
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#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE86CD4
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#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE86CD8
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#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE86CDC
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#define mmTPC2_CFG_QM_TENSOR_13_PADDING_VALUE 0xE86CE0
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#define mmTPC2_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE86CE4
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#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE86CE8
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#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE86CEC
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#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE86CF0
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#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE86CF4
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#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE86CF8
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#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE86CFC
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#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE86D00
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#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE86D04
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#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE86D08
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#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE86D0C
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#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE86D10
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#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE86D14
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#define mmTPC2_CFG_QM_TENSOR_14_PADDING_VALUE 0xE86D18
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#define mmTPC2_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE86D1C
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#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE86D20
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#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE86D24
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#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE86D28
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#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE86D2C
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#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE86D30
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#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE86D34
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#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE86D38
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#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE86D3C
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#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE86D40
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#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE86D44
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#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE86D48
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#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE86D4C
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#define mmTPC2_CFG_QM_TENSOR_15_PADDING_VALUE 0xE86D50
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#define mmTPC2_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE86D54
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#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE86D58
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#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE86D5C
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#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE86D60
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#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE86D64
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#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE86D68
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#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE86D6C
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#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE86D70
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#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE86D74
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#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE86D78
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#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE86D7C
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#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D80
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#define mmTPC2_CFG_QM_SYNC_OBJECT_ADDR 0xE86D84
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#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86D88
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#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86D8C
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#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86D90
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#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86D94
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#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86D98
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#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86D9C
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#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86DA0
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#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86DA4
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#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86DA8
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#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86DAC
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#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86DB0
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#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86DB4
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#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86DB8
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#define mmTPC2_CFG_QM_KERNEL_ID 0xE86DBC
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#define mmTPC2_CFG_QM_SRF_0 0xE86DC0
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#define mmTPC2_CFG_QM_SRF_1 0xE86DC4
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#define mmTPC2_CFG_QM_SRF_2 0xE86DC8
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#define mmTPC2_CFG_QM_SRF_3 0xE86DCC
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#define mmTPC2_CFG_QM_SRF_4 0xE86DD0
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#define mmTPC2_CFG_QM_SRF_5 0xE86DD4
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#define mmTPC2_CFG_QM_SRF_6 0xE86DD8
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#define mmTPC2_CFG_QM_SRF_7 0xE86DDC
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#define mmTPC2_CFG_QM_SRF_8 0xE86DE0
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#define mmTPC2_CFG_QM_SRF_9 0xE86DE4
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#define mmTPC2_CFG_QM_SRF_10 0xE86DE8
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#define mmTPC2_CFG_QM_SRF_11 0xE86DEC
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#define mmTPC2_CFG_QM_SRF_12 0xE86DF0
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#define mmTPC2_CFG_QM_SRF_13 0xE86DF4
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#define mmTPC2_CFG_QM_SRF_14 0xE86DF8
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#define mmTPC2_CFG_QM_SRF_15 0xE86DFC
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#define mmTPC2_CFG_QM_SRF_16 0xE86E00
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#define mmTPC2_CFG_QM_SRF_17 0xE86E04
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#define mmTPC2_CFG_QM_SRF_18 0xE86E08
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#define mmTPC2_CFG_QM_SRF_19 0xE86E0C
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#define mmTPC2_CFG_QM_SRF_20 0xE86E10
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#define mmTPC2_CFG_QM_SRF_21 0xE86E14
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#define mmTPC2_CFG_QM_SRF_22 0xE86E18
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#define mmTPC2_CFG_QM_SRF_23 0xE86E1C
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#define mmTPC2_CFG_QM_SRF_24 0xE86E20
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#define mmTPC2_CFG_QM_SRF_25 0xE86E24
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#define mmTPC2_CFG_QM_SRF_26 0xE86E28
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#define mmTPC2_CFG_QM_SRF_27 0xE86E2C
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#define mmTPC2_CFG_QM_SRF_28 0xE86E30
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#define mmTPC2_CFG_QM_SRF_29 0xE86E34
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#define mmTPC2_CFG_QM_SRF_30 0xE86E38
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#define mmTPC2_CFG_QM_SRF_31 0xE86E3C
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#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */
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