/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#ifdef INCLUDE_PROC
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process(PROC_HOST, #host_init, #host_recv)
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#endif
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/******************************************************************************
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* HOST data segment
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*****************************************************************************/
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#ifdef INCLUDE_DATA
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// HOST (R)FIFO packet format
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.equ #fifo_process 0x00
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.equ #fifo_message 0x04
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.equ #fifo_data0 0x08
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.equ #fifo_data1 0x0c
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// HOST HOST->PWR queue description
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.equ #fifo_qlen 4 // log2(size of queue entry in bytes)
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.equ #fifo_qnum 3 // log2(max number of entries in queue)
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.equ #fifo_qmaskb (1 << #fifo_qnum) // max number of entries in queue
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.equ #fifo_qmaskp (#fifo_qmaskb - 1)
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.equ #fifo_qmaskf ((#fifo_qmaskb << 1) - 1)
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.equ #fifo_qsize (1 << (#fifo_qlen + #fifo_qnum))
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fifo_queue: .skip 128 // #fifo_qsize
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// HOST PWR->HOST queue description
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.equ #rfifo_qlen 4 // log2(size of queue entry in bytes)
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.equ #rfifo_qnum 3 // log2(max number of entries in queue)
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.equ #rfifo_qmaskb (1 << #rfifo_qnum) // max number of entries in queue
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.equ #rfifo_qmaskp (#rfifo_qmaskb - 1)
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.equ #rfifo_qmaskf ((#rfifo_qmaskb << 1) - 1)
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.equ #rfifo_qsize (1 << (#rfifo_qlen + #rfifo_qnum))
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rfifo_queue: .skip 128 // #rfifo_qsize
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#endif
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/******************************************************************************
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* HOST code segment
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*****************************************************************************/
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#ifdef INCLUDE_CODE
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// HOST->PWR comms - dequeue message(s) for process(es) from FIFO
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//
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// $r15 - current (host)
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// $r0 - zero
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host_send:
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nv_iord($r1, NV_PPWR_FIFO_GET(0))
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nv_iord($r2, NV_PPWR_FIFO_PUT(0))
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cmp b32 $r1 $r2
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bra e #host_send_done
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// calculate address of message
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and $r14 $r1 #fifo_qmaskp
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shl b32 $r14 $r14 #fifo_qlen
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add b32 $r14 #fifo_queue
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// read message data, and pass to appropriate process
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ld b32 $r11 D[$r14 + #fifo_data1]
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ld b32 $r12 D[$r14 + #fifo_data0]
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ld b32 $r13 D[$r14 + #fifo_message]
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ld b32 $r14 D[$r14 + #fifo_process]
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call(send)
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// increment GET
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add b32 $r1 0x1
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and $r14 $r1 #fifo_qmaskf
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nv_iowr(NV_PPWR_FIFO_GET(0), $r14)
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bra #host_send
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host_send_done:
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ret
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// PWR->HOST comms - enqueue message for HOST to RFIFO
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//
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// $r15 - current (host)
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// $r14 - process
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// $r13 - message
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// $r12 - message data 0
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// $r11 - message data 1
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// $r0 - zero
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host_recv:
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// message from intr handler == HOST->PWR comms pending
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imm32($r1, PROC_KERN)
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cmp b32 $r14 $r1
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bra e #host_send
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// wait for space in RFIFO
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host_recv_wait:
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nv_iord($r1, NV_PPWR_RFIFO_GET)
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nv_iord($r2, NV_PPWR_RFIFO_PUT)
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xor $r1 #rfifo_qmaskb
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cmp b32 $r1 $r2
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bra e #host_recv_wait
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and $r3 $r2 #rfifo_qmaskp
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shl b32 $r3 #rfifo_qlen
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add b32 $r3 #rfifo_queue
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// enqueue message
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st b32 D[$r3 + #fifo_data1] $r11
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st b32 D[$r3 + #fifo_data0] $r12
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st b32 D[$r3 + #fifo_message] $r13
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st b32 D[$r3 + #fifo_process] $r14
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add b32 $r2 0x1
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and $r2 #rfifo_qmaskf
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nv_iowr(NV_PPWR_RFIFO_PUT, $r2)
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// notify host of pending message
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mov $r2 NV_PPWR_INTR_TRIGGER_USER0
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nv_iowr(NV_PPWR_INTR_TRIGGER, $r2)
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ret
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// $r15 - current (host)
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// $r0 - zero
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host_init:
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// store each fifo's base/size in H2D/D2H scratch regs
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mov $r1 #fifo_qsize
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shl b32 $r1 16
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or $r1 #fifo_queue
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nv_iowr(NV_PPWR_H2D, $r1);
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mov $r1 #rfifo_qsize
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shl b32 $r1 16
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or $r1 #rfifo_queue
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nv_iowr(NV_PPWR_D2H, $r1);
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// enable fifo subintr for first fifo
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mov $r1 1
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nv_iowr(NV_PPWR_FIFO_INTR_EN, $r1)
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ret
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#endif
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