/* fuc microcode for gf100 PGRAPH/HUB
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*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#ifdef INCLUDE_DATA
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hub_mmio_list_head: .b32 #hub_mmio_list_base
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hub_mmio_list_tail: .b32 #hub_mmio_list_next
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gpc_count: .b32 0
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rop_count: .b32 0
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cmd_queue: queue_init
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ctx_current: .b32 0
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.align 256
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chan_data:
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chan_mmio_count: .b32 0
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chan_mmio_address: .b32 0
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.align 256
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xfer_data: .skip 256
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hub_mmio_list_base:
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.b32 0x0417e91c // 0x17e91c, 2
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hub_mmio_list_next:
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#endif
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#ifdef INCLUDE_CODE
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// reports an exception to the host
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//
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// In: $r15 error code (see os.h)
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//
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error:
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nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)
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mov $r15 1
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nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15)
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ret
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// HUB fuc initialisation, executed by triggering ucode start, will
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// fall through to main loop after completion.
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//
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// Output:
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// CC_SCRATCH[0]:
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// 31:31: set to signal completion
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// CC_SCRATCH[1]:
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// 31:0: total PGRAPH context size
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//
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init:
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clear b32 $r0
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mov $xdbase $r0
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// setup stack
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nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0)
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extr $r1 $r1 9:17
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shl b32 $r1 8
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mov $sp $r1
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// enable fifo access
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mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO
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nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2)
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// setup i0 handler, and route all interrupts to it
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mov $r1 #ih
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mov $iv0 $r1
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clear b32 $r2
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nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2)
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// route HUB_CHSW_PULSE to fuc interrupt 8
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mov $r2 0x2003 // { HUB_CHSW_PULSE, ZERO } -> intr 8
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nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2)
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// not sure what these are, route them because NVIDIA does, and
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// the IRQ handler will signal the host if we ever get one.. we
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// may find out if/why we need to handle these if so..
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//
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mov $r2 0x2004 // { 0x04, ZERO } -> intr 9
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nv_iowr(NV_PGRAPH_FECS_IROUTE, 1, $r2)
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mov $r2 0x200b // { HUB_FIRMWARE_MTHD, ZERO } -> intr 10
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nv_iowr(NV_PGRAPH_FECS_IROUTE, 2, $r2)
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mov $r2 0x200c // { 0x0c, ZERO } -> intr 15
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nv_iowr(NV_PGRAPH_FECS_IROUTE, 7, $r2)
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// enable all INTR_UP interrupts
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sub b32 $r3 $r0 1
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nv_iowr(NV_PGRAPH_FECS_INTR_UP_EN, 0, $r3)
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// enable fifo, ctxsw, 9, fwmthd, 15 interrupts
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imm32($r2, 0x8704)
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nv_iowr(NV_PGRAPH_FECS_INTR_EN_SET, 0, $r2)
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// fifo level triggered, rest edge
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mov $r2 NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL
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nv_iowr(NV_PGRAPH_FECS_INTR_MODE, 0, $r2)
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// enable interrupts
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bset $flags ie0
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// fetch enabled GPC/ROP counts
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nv_rd32($r14, 0x409604)
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extr $r1 $r15 16:20
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st b32 D[$r0 + #rop_count] $r1
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and $r15 0x1f
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st b32 D[$r0 + #gpc_count] $r15
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// set BAR_REQMASK to GPC mask
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mov $r1 1
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shl b32 $r1 $r15
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sub b32 $r1 1
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nv_iowr(NV_PGRAPH_FECS_BAR_MASK0, 0, $r1)
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nv_iowr(NV_PGRAPH_FECS_BAR_MASK1, 0, $r1)
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// context size calculation, reserve first 256 bytes for use by fuc
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mov $r1 256
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//
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mov $r15 2
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call(ctx_4170s)
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call(ctx_4170w)
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mov $r15 0x10
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call(ctx_86c)
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// calculate size of mmio context data
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ld b32 $r14 D[$r0 + #hub_mmio_list_head]
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ld b32 $r15 D[$r0 + #hub_mmio_list_tail]
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call(mmctx_size)
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// set mmctx base addresses now so we don't have to do it later,
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// they don't (currently) ever change
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shr b32 $r4 $r1 8
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nv_iowr(NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE, 0, $r4)
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nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE, 0, $r4)
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add b32 $r3 0x1300
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add b32 $r1 $r15
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shr b32 $r15 2
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nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_COUNT, 0, $r15) // wtf??
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// strands, base offset needs to be aligned to 256 bytes
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shr b32 $r1 8
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add b32 $r1 1
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shl b32 $r1 8
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mov b32 $r15 $r1
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call(strand_ctx_init)
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add b32 $r1 $r15
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// initialise each GPC in sequence by passing in the offset of its
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// context data in GPCn_CC_SCRATCH[1], and starting its FUC (which
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// has previously been uploaded by the host) running.
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//
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// the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31
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// when it has completed, and return the size of its context data
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// in GPCn_CC_SCRATCH[1]
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//
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ld b32 $r3 D[$r0 + #gpc_count]
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imm32($r4, 0x502000)
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init_gpc:
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// setup, and start GPC ucode running
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add b32 $r14 $r4 0x804
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mov b32 $r15 $r1
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call(nv_wr32) // CC_SCRATCH[1] = ctx offset
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add b32 $r14 $r4 0x10c
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clear b32 $r15
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call(nv_wr32)
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add b32 $r14 $r4 0x104
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call(nv_wr32) // ENTRY
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add b32 $r14 $r4 0x100
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mov $r15 2 // CTRL_START_TRIGGER
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call(nv_wr32) // CTRL
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// wait for it to complete, and adjust context size
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add b32 $r14 $r4 0x800
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init_gpc_wait:
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call(nv_rd32)
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xbit $r15 $r15 31
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bra e #init_gpc_wait
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add b32 $r14 $r4 0x804
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call(nv_rd32)
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add b32 $r1 $r15
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// next!
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add b32 $r4 0x8000
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sub b32 $r3 1
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bra ne #init_gpc
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//
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mov $r15 0
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call(ctx_86c)
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mov $r15 0
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call(ctx_4170s)
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// save context size, and tell host we're ready
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nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1)
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clear b32 $r1
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bset $r1 31
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nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1)
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// Main program loop, very simple, sleeps until woken up by the interrupt
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// handler, pulls a command from the queue and executes its handler
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//
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wait:
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// sleep until we have something to do
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sleep $p0
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bset $flags $p0
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main:
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mov $r13 #cmd_queue
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call(queue_get)
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bra $p1 #wait
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// context switch, requested by GPU?
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cmpu b32 $r14 0x4001
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bra ne #main_not_ctx_switch
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trace_set(T_AUTO)
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nv_iord($r1, NV_PGRAPH_FECS_CHAN_ADDR, 0)
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nv_iord($r2, NV_PGRAPH_FECS_CHAN_NEXT, 0)
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xbit $r3 $r1 31
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bra e #chsw_no_prev
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xbit $r3 $r2 31
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bra e #chsw_prev_no_next
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push $r2
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mov b32 $r2 $r1
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trace_set(T_SAVE)
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bclr $flags $p1
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bset $flags $p2
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call(ctx_xfer)
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trace_clr(T_SAVE);
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pop $r2
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trace_set(T_LOAD);
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bset $flags $p1
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call(ctx_xfer)
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trace_clr(T_LOAD);
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bra #chsw_done
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chsw_prev_no_next:
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push $r2
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mov b32 $r2 $r1
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bclr $flags $p1
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bclr $flags $p2
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call(ctx_xfer)
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pop $r2
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nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2)
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bra #chsw_done
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chsw_no_prev:
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xbit $r3 $r2 31
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bra e #chsw_done
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bset $flags $p1
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bclr $flags $p2
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call(ctx_xfer)
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// ack the context switch request
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chsw_done:
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mov $r2 NV_PGRAPH_FECS_CHSW_ACK
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nv_iowr(NV_PGRAPH_FECS_CHSW, 0, $r2)
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trace_clr(T_AUTO)
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bra #main
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// request to set current channel? (*not* a context switch)
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main_not_ctx_switch:
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cmpu b32 $r14 0x0001
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bra ne #main_not_ctx_chan
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mov b32 $r2 $r15
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call(ctx_chan)
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bra #main_done
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// request to store current channel context?
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main_not_ctx_chan:
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cmpu b32 $r14 0x0002
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bra ne #main_not_ctx_save
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trace_set(T_SAVE)
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bclr $flags $p1
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bclr $flags $p2
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call(ctx_xfer)
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trace_clr(T_SAVE)
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bra #main_done
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main_not_ctx_save:
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shl b32 $r15 $r14 16
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or $r15 E_BAD_COMMAND
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call(error)
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bra #main
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main_done:
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clear b32 $r2
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bset $r2 31
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nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2)
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bra #main
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// interrupt handler
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ih:
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push $r0
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push $r8
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mov $r8 $flags
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push $r8
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push $r9
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push $r10
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push $r11
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push $r13
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push $r14
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push $r15
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clear b32 $r0
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// incoming fifo command?
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nv_iord($r10, NV_PGRAPH_FECS_INTR, 0)
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and $r11 $r10 NV_PGRAPH_FECS_INTR_FIFO
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bra e #ih_no_fifo
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// queue incoming fifo command for later processing
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mov $r13 #cmd_queue
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nv_iord($r14, NV_PGRAPH_FECS_FIFO_CMD, 0)
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nv_iord($r15, NV_PGRAPH_FECS_FIFO_DATA, 0)
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call(queue_put)
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add b32 $r11 0x400
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mov $r14 1
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nv_iowr(NV_PGRAPH_FECS_FIFO_ACK, 0, $r14)
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// context switch request?
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ih_no_fifo:
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and $r11 $r10 NV_PGRAPH_FECS_INTR_CHSW
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bra e #ih_no_ctxsw
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// enqueue a context switch for later processing
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mov $r13 #cmd_queue
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mov $r14 0x4001
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call(queue_put)
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// firmware method?
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ih_no_ctxsw:
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and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD
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bra e #ih_no_fwmthd
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// none we handle; report to host and ack
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nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO)
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nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15)
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nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR)
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nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15)
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extr $r14 $r15 16:18
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shl b32 $r14 $r14 2
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imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0))
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add b32 $r14 $r15
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call(nv_rd32)
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nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15)
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mov $r15 E_BAD_FWMTHD
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call(error)
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mov $r11 0x100
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nv_wr32(0x400144, $r11)
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// anything we didn't handle, bring it to the host's attention
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ih_no_fwmthd:
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mov $r11 0x504 // FIFO | CHSW | FWMTHD
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not b32 $r11
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and $r11 $r10 $r11
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bra e #ih_no_other
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nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r11)
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// ack, and wake up main()
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ih_no_other:
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nv_iowr(NV_PGRAPH_FECS_INTR_ACK, 0, $r10)
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pop $r15
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pop $r14
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pop $r13
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pop $r11
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pop $r10
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pop $r9
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pop $r8
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mov $flags $r8
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pop $r8
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pop $r0
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bclr $flags $p0
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iret
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#if CHIPSET < GK100
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// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
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ctx_4160s:
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mov $r15 1
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nv_wr32(0x404160, $r15)
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ctx_4160s_wait:
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nv_rd32($r15, 0x404160)
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xbit $r15 $r15 4
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bra e #ctx_4160s_wait
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ret
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// Without clearing again at end of xfer, some things cause PGRAPH
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// to hang with STATUS=0x00000007 until it's cleared.. fbcon can
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// still function with it set however...
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ctx_4160c:
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clear b32 $r15
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nv_wr32(0x404160, $r15)
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ret
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#endif
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// Again, not real sure
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//
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// In: $r15 value to set 0x404170 to
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//
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ctx_4170s:
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or $r15 0x10
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nv_wr32(0x404170, $r15)
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ret
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// Waits for a ctx_4170s() call to complete
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//
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ctx_4170w:
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nv_rd32($r15, 0x404170)
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and $r15 0x10
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bra ne #ctx_4170w
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ret
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// Disables various things, waits a bit, and re-enables them..
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//
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// Not sure how exactly this helps, perhaps "ENABLE" is not such a
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// good description for the bits we turn off? Anyways, without this,
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// funny things happen.
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//
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ctx_redswitch:
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mov $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC
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or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP
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or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC
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or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN
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nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14)
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mov $r15 8
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ctx_redswitch_delay:
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sub b32 $r15 1
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bra ne #ctx_redswitch_delay
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or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP
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or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN
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nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14)
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ret
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// Not a clue what this is for, except that unless the value is 0x10, the
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// strand context is saved (and presumably restored) incorrectly..
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//
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// In: $r15 value to set to (0x00/0x10 are used)
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//
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ctx_86c:
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nv_iowr(NV_PGRAPH_FECS_UNK86C, 0, $r15)
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nv_wr32(0x408a14, $r15)
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nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15)
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ret
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// In: $r15 NV_PGRAPH_FECS_MEM_CMD_*
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ctx_mem:
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nv_iowr(NV_PGRAPH_FECS_MEM_CMD, 0, $r15)
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ctx_mem_wait:
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nv_iord($r15, NV_PGRAPH_FECS_MEM_CMD, 0)
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or $r15 $r15
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bra ne #ctx_mem_wait
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ret
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// ctx_load - load's a channel's ctxctl data, and selects its vm
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//
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// In: $r2 channel address
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//
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ctx_load:
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trace_set(T_CHAN)
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// switch to channel, somewhat magic in parts..
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mov $r10 12 // DONE_UNK12
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call(wait_donez)
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clear b32 $r15
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nv_iowr(0x409a24, 0, $r15)
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nv_iowr(NV_PGRAPH_FECS_CHAN_NEXT, 0, $r2)
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nv_iowr(NV_PGRAPH_FECS_MEM_CHAN, 0, $r2)
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mov $r15 NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN
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call(ctx_mem)
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nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2)
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// load channel header, fetch PGRAPH context pointer
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mov $xtargets $r0
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bclr $r2 31
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shl b32 $r2 4
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add b32 $r2 2
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trace_set(T_LCHAN)
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nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r2)
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imm32($r2, NV_PGRAPH_FECS_MEM_TARGET_UNK31)
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or $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM
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nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2)
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mov $r1 0x10 // chan + 0x0210
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mov $r2 #xfer_data
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sethi $r2 0x00020000 // 16 bytes
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xdld $r1 $r2
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xdwait
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trace_clr(T_LCHAN)
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// update current context
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ld b32 $r1 D[$r0 + #xfer_data + 4]
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shl b32 $r1 24
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ld b32 $r2 D[$r0 + #xfer_data + 0]
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shr b32 $r2 8
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or $r1 $r2
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st b32 D[$r0 + #ctx_current] $r1
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// set transfer base to start of context, and fetch context header
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trace_set(T_LCTXH)
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nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r1)
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mov $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VM
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nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2)
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mov $r1 #chan_data
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sethi $r1 0x00060000 // 256 bytes
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xdld $r0 $r1
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xdwait
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trace_clr(T_LCTXH)
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trace_clr(T_CHAN)
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ret
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// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as
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// the active channel for ctxctl, but not actually transfer
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// any context data. intended for use only during initial
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// context construction.
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//
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// In: $r2 channel address
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//
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ctx_chan:
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#if CHIPSET < GK100
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call(ctx_4160s)
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#endif
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call(ctx_load)
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mov $r10 12 // DONE_UNK12
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call(wait_donez)
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mov $r15 5 // MEM_CMD 5 ???
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call(ctx_mem)
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#if CHIPSET < GK100
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call(ctx_4160c)
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#endif
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ret
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// Execute per-context state overrides list
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//
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// Only executed on the first load of a channel. Might want to look into
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// removing this and having the host directly modify the channel's context
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// to change this state... The nouveau DRM already builds this list as
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// it's definitely needed for NVIDIA's, so we may as well use it for now
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//
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// Input: $r1 mmio list length
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//
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ctx_mmio_exec:
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// set transfer base to be the mmio list
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ld b32 $r3 D[$r0 + #chan_mmio_address]
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nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3)
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clear b32 $r3
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ctx_mmio_loop:
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// fetch next 256 bytes of mmio list if necessary
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and $r4 $r3 0xff
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bra ne #ctx_mmio_pull
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mov $r5 #xfer_data
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sethi $r5 0x00060000 // 256 bytes
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xdld $r3 $r5
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xdwait
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// execute a single list entry
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ctx_mmio_pull:
|
ld b32 $r14 D[$r4 + #xfer_data + 0x00]
|
ld b32 $r15 D[$r4 + #xfer_data + 0x04]
|
call(nv_wr32)
|
|
// next!
|
add b32 $r3 8
|
sub b32 $r1 1
|
bra ne #ctx_mmio_loop
|
|
// set transfer base back to the current context
|
ctx_mmio_done:
|
ld b32 $r3 D[$r0 + #ctx_current]
|
nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3)
|
|
// disable the mmio list now, we don't need/want to execute it again
|
st b32 D[$r0 + #chan_mmio_count] $r0
|
mov $r1 #chan_data
|
sethi $r1 0x00060000 // 256 bytes
|
xdst $r0 $r1
|
xdwait
|
ret
|
|
// Transfer HUB context data between GPU and storage area
|
//
|
// In: $r2 channel address
|
// $p1 clear on save, set on load
|
// $p2 set if opposite direction done/will be done, so:
|
// on save it means: "a load will follow this save"
|
// on load it means: "a save preceeded this load"
|
//
|
ctx_xfer:
|
// according to mwk, some kind of wait for idle
|
mov $r14 4
|
nv_iowr(0x409c08, 0, $r14)
|
ctx_xfer_idle:
|
nv_iord($r14, 0x409c00, 0)
|
and $r14 0x2000
|
bra ne #ctx_xfer_idle
|
|
bra not $p1 #ctx_xfer_pre
|
bra $p2 #ctx_xfer_pre_load
|
ctx_xfer_pre:
|
mov $r15 0x10
|
call(ctx_86c)
|
#if CHIPSET < GK100
|
call(ctx_4160s)
|
#endif
|
bra not $p1 #ctx_xfer_exec
|
|
ctx_xfer_pre_load:
|
mov $r15 2
|
call(ctx_4170s)
|
call(ctx_4170w)
|
call(ctx_redswitch)
|
clear b32 $r15
|
call(ctx_4170s)
|
call(ctx_load)
|
|
// fetch context pointer, and initiate xfer on all GPCs
|
ctx_xfer_exec:
|
ld b32 $r1 D[$r0 + #ctx_current]
|
|
clear b32 $r2
|
nv_iowr(NV_PGRAPH_FECS_BAR, 0, $r2)
|
|
nv_wr32(0x41a500, $r1) // GPC_BCAST_WRCMD_DATA = ctx pointer
|
xbit $r15 $flags $p1
|
xbit $r2 $flags $p2
|
shl b32 $r2 1
|
or $r15 $r2
|
nv_wr32(0x41a504, $r15) // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
|
|
// strands
|
call(strand_pre)
|
clear b32 $r2
|
nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r2)
|
xbit $r2 $flags $p1 // SAVE/LOAD
|
add b32 $r2 NV_PGRAPH_FECS_STRAND_CMD_SAVE
|
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r2)
|
|
// mmio context
|
xbit $r10 $flags $p1 // direction
|
or $r10 6 // first, last
|
mov $r11 0 // base = 0
|
ld b32 $r12 D[$r0 + #hub_mmio_list_head]
|
ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
|
mov $r14 0 // not multi
|
call(mmctx_xfer)
|
|
// wait for GPCs to all complete
|
mov $r10 8 // DONE_BAR
|
call(wait_doneo)
|
|
// wait for strand xfer to complete
|
call(strand_wait)
|
|
// post-op
|
bra $p1 #ctx_xfer_post
|
mov $r10 12 // DONE_UNK12
|
call(wait_donez)
|
mov $r15 5 // MEM_CMD 5 ???
|
call(ctx_mem)
|
|
bra $p2 #ctx_xfer_done
|
ctx_xfer_post:
|
mov $r15 2
|
call(ctx_4170s)
|
clear b32 $r15
|
call(ctx_86c)
|
call(strand_post)
|
call(ctx_4170w)
|
clear b32 $r15
|
call(ctx_4170s)
|
|
bra not $p1 #ctx_xfer_no_post_mmio
|
ld b32 $r1 D[$r0 + #chan_mmio_count]
|
or $r1 $r1
|
bra e #ctx_xfer_no_post_mmio
|
call(ctx_mmio_exec)
|
|
ctx_xfer_no_post_mmio:
|
#if CHIPSET < GK100
|
call(ctx_4160c)
|
#endif
|
|
ctx_xfer_done:
|
ret
|
#endif
|
