/** @file
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Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
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Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef OGMA_REG_H
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#define OGMA_REG_H
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#include "ogma_reg_netsec.h"
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#include "ogma_reg_f_gmac_4mt.h"
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/* aliases */
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#define OGMA_REG_ADDR_TOP_INTEN OGMA_REG_ADDR_TOP_INTEN_A
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#define OGMA_REG_ADDR_TOP_INTEN_SET OGMA_REG_ADDR_TOP_INTEN_A_SET
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#define OGMA_REG_ADDR_TOP_INTEN_CLR OGMA_REG_ADDR_TOP_INTEN_A_CLR
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/* aliases end here */
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/* need fixing */
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#define OGMA_REG_ADDR_DMAC_MH_CMD_BUF (0x87)
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/*bit fields for PKT_CTRL*/
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#define OGMA_PKT_CTRL_REG_EN_JUMBO (1UL << 27)
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#define OGMA_PKT_CTRL_REG_EN_BITPATF (1UL << 4 )
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#define OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER (1UL << 3 )
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#define OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE (1UL << 2 )
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#define OGMA_PKT_CTRL_REG_LOG_HD_ER (1UL << 1 )
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#define OGMA_PKT_CTRL_REG_DRP_NO_MATCH (1UL << 0 )
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#define OGMA_CLK_EN_REG_DOM_G (1UL << 5)
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/************************************************************
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* Bit fields
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************************************************************/
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/* bit fields for com_init */
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#define OGMA_COM_INIT_REG_DB (1UL << 2)
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#define OGMA_COM_INIT_REG_CLS (1UL << 1)
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#define OGMA_COM_INIT_REG_ALL ( OGMA_COM_INIT_REG_CLS | OGMA_COM_INIT_REG_DB)
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/* bit fields for soft_rst */
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#define OGMA_SOFT_RST_REG_RESET (0)
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#define OGMA_SOFT_RST_REG_RUN (1UL << 31)
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/* bit fields for dma_hm_ctrl */
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#define OGMA_DMA_CTRL_REG_STOP 1UL
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/* bit fields for gmac_cmd */
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#define OGMA_GMAC_CMD_ST_READ (0)
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#define OGMA_GMAC_CMD_ST_WRITE (1UL << 28)
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#define OGMA_GMAC_CMD_ST_BUSY (1UL << 31)
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/* bit fields for F_GMAC4MT BMR*/
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#define OGMA_GMAC_BMR_REG_COMMON (0x00412080)
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#define OGMA_GMAC_BMR_REG_RESET (0x00020181)
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#define OGMA_GMAC_BMR_REG_SWR (0x00000001)
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/* bit fields for F_GMAC4MT OMR*/
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#define OGMA_GMAC_OMR_REG_ST (1UL << 13)
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#define OGMA_GMAC_OMR_REG_SR (1UL << 1)
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/* bit fields for F_GMAC4MT MCR*/
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#define OGMA_GMAC_MCR_REG_CST (1UL << 25)
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#define OGMA_GMAC_MCR_REG_JE (1UL << 20)
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#define OGMA_GMAC_MCR_REG_PS (1UL << 15)
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#define OGMA_GMAC_MCR_REG_FES (1UL << 14)
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#define OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON (0x0000280c)
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#define OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON (0x0001a00c)
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#define OGMA_GMAC_MCR_1G_FULL ( OGMA_GMAC_MCR_REG_CST | \
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OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
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#define OGMA_GMAC_MCR_100M_FULL ( OGMA_GMAC_MCR_REG_CST | \
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OGMA_GMAC_MCR_REG_PS | \
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OGMA_GMAC_MCR_REG_FES | \
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OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
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#define OGMA_GMAC_MCR_100M_HALF ( OGMA_GMAC_MCR_REG_CST | \
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OGMA_GMAC_MCR_REG_FES | \
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OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
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#define OGMA_GMAC_MCR_10M_FULL ( OGMA_GMAC_MCR_REG_CST | \
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OGMA_GMAC_MCR_REG_PS | \
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OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
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#define OGMA_GMAC_MCR_10M_HALF ( OGMA_GMAC_MCR_REG_CST | \
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OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
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/*bit fields for F_GMAC4MT FCR*/
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#define OGMA_GMAC_FCR_REG_RFE (1UL << 2)
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#define OGMA_GMAC_FCR_REG_TFE (1UL << 1)
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/* bit fields for F_GMAC4MT GAR */
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#define OGMA_GMAC_GAR_REG_GW (1UL << 1)
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#define OGMA_GMAC_GAR_REG_GB (1UL << 0)
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/* bit fields for F_GMAC4MT RDLAR*/
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#define OGMA_GMAC_RDLAR_REG_COMMON (0x00018000UL)
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/* bit fields for F_GMAC4MT TDLAR*/
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#define OGMA_GMAC_TDLAR_REG_COMMON (0x0001c000UL)
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#define OGMA_GMAC_GAR_REG_SHIFT_PA (11)
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#define OGMA_GMAC_GAR_REG_SHIFT_GR (6)
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#define OGMA_GMAC_GAR_REG_SHIFT_CR (2)
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#define OGMA_GMAC_GAR_REG_CR_25_35_MHZ (2)
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#define OGMA_GMAC_GAR_REG_CR_35_60_MHZ (3)
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#define OGMA_GMAC_GAR_REG_CR_60_100_MHZ (0)
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#define OGMA_GMAC_GAR_REG_CR_100_150_MHZ (1)
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#define OGMA_GMAC_GAR_REG_CR_150_250_MHZ (4)
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#define OGMA_GMAC_GAR_REG_CR_250_300_MHZ (5)
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/* bit fields for F_GMAC4MT LPITCR */
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#define OGMA_GMAC_LPITCR_REG_LIT (16)
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#define OGMA_GMAC_LPITCR_REG_TWT (0)
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/* bit fileds mask for F_GMAC4MT LPITCR */
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#define OGMA_GMAC_LPITCR_REG_MASK_LIT (0x3ffU)
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#define OGMA_GMAC_LPITCR_REG_MASK_TWT (0xffffU)
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/**
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* PHY regtister Address
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*/
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#define OGMA_PHY_REG_ADDR_CONTROL 0
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#define OGMA_PHY_REG_ADDR_STATUS 1U
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#define OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY 4U
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#define OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY 5U
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#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL 9U
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#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS 10U
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#define OGMA_PHY_REG_ADDR_MMD_AC 13U
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#define OGMA_PHY_REG_ADDR_MMD_AAD 14U
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/* bit fields for PHY CONTROL Register */
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#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB (6)
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#define OGMA_PHY_CONTROL_REG_DUPLEX_MODE (8)
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#define OGMA_PHY_CONTROL_REG_ISOLATE (10)
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#define OGMA_PHY_CONTROL_REG_POWER_DOWN (11)
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#define OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE (12)
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#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB (13)
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#define OGMA_PHY_CONTROL_REG_LOOPBACK (14)
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#define OGMA_PHY_CONTROL_REG_RESET (15)
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/* bit fields for PHY STATUS Register */
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#define OGMA_PHY_STATUS_REG_LINK_STATUS (2)
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#define OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY (3)
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#define OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP (5)
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/* bit fields for PHY MASTER-SLAVE Control Register */
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#define OGMA_PHY_MSC_REG_1000BASE_FULL (9)
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#define OGMA_PHY_MSC_REG_1000BASE_HALF (8)
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/* bit fields for PHY MASTER-SLAVE Status Register */
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#define OGMA_PHY_MSS_REG_LP_1000BASE_FULL (11)
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#define OGMA_PHY_MSS_REG_LP_1000BASE_HALF (10)
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/* bit fields for PHY Auto-Negotiation Advertisement Register */
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#define OGMA_PHY_ANA_REG_TAF (5)
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/* bit fileds mask for F_GMAC4MT LPITCR */
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#define OGMA_PHY_ANA_REG_TAF_MASK (0x7fU)
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/* bit fields for PHY Technology Ability Field */
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#define OGMA_PHY_TAF_REG_100BASE_FULL (1U << 3)
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#define OGMA_PHY_TAF_REG_100BASE_HALF (1U << 2)
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#define OGMA_PHY_TAF_REG_10BASE_FULL (1U << 1)
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#define OGMA_PHY_TAF_REG_10BASE_HALF (1U << 0)
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/**
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* PHY Device Address
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*/
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#define OGMA_PHY_DEV_ADDR_AUTO_NEGO (7U)
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/**
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* PHY Register Address for Device Address 7
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*/
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#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE (60U)
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#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY (61U)
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/* bit fields for PHY AutoNegotiation Field */
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#define OGMA_PHY_AUTO_NEGO_1000BASE_EEE (1U << 2)
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#define OGMA_PHY_AUTO_NEGO_100BASE_EEE (1U << 1)
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/* bit fields for DESC RING CONFIG */
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#define OGMA_REG_DESC_RING_CONFIG_CFG_UP (31)
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#define OGMA_REG_DESC_RING_CONFIG_CH_RST (30)
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#define OGMA_REG_DESC_RING_CONFIG_TMR_MODE (4)
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#define OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN (0)
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/* bit fields for mac_desc_soft_rst */
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#define OGMA_MAC_DESC_SOFT_RST_SOFT_RST 1UL
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/* bit fields for mac_desc_init */
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#define OGMA_MAC_DESC_INIT_REG_INIT 1UL
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/* bit fields for dis_core */
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#define OGMA_DIS_CORE_REG_DIS_PCORE (1UL << 2)
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#define OGMA_DIS_CORE_REG_DIS_MHCORE (1UL << 1)
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#define OGMA_DIS_CORE_REG_DIS_HMCORE (1UL << 0)
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#define OGMA_DIS_CORE_REG_ALL ( OGMA_DIS_CORE_REG_DIS_HMCORE | \
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OGMA_DIS_CORE_REG_DIS_MHCORE | \
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OGMA_DIS_CORE_REG_DIS_PCORE)
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/* bit fields for dma_info */
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#define OGMA_DMA_INFO_REG_AXI_WRITE_BUSY (1UL << 3)
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#define OGMA_DMA_INFO_REG_AXI_READ_BUSY (1UL << 2)
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#define OGMA_DMA_INFO_REG_AXI_BUSY ( OGMA_DMA_INFO_REG_AXI_WRITE_BUSY | \
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OGMA_DMA_INFO_REG_AXI_READ_BUSY)
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#endif /*OGMA_REG_H*/
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