/** @file
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Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
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Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef OGMA_INTERNAL_H
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#define OGMA_INTERNAL_H
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#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
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#include "ogma_reg.h"
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#include "pfdep.h"
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/* Just a million to prevent typing errors. */
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#define OGMA_CLK_MHZ (1000000)
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#define OGMA_INSTANCE_NUM_MAX 1
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#define OGMA_RX_PKT_BUF_LEN 1522
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#define OGMA_RX_JUMBO_PKT_BUF_LEN 9022
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#define OGMA_DUMMY_DESC_ENTRY_LEN 48
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#define OGMA_REG_ADDR_CLK_EN OGMA_REG_ADDR_CLK_EN_0
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extern const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
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extern const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
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extern const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
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extern const ogma_uint32 ogma_desc_start_reg_addr[OGMA_DESC_RING_ID_MAX+1];
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typedef struct ogma_ctrl_s ogma_ctrl_t;
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typedef struct ogma_desc_ring_s ogma_desc_ring_t;
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typedef struct ogma_clk_ctrl_s ogma_clk_ctrl_t;
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typedef union ogma_desc_entry_priv_u ogma_desc_entry_priv_t;
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struct ogma_clk_ctrl_s{
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ogma_uint8 mac_req_num;
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};
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struct ogma_desc_ring_s{
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ogma_desc_ring_id_t ring_id;
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ogma_desc_ring_param_t param;
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ogma_uint rx_desc_ring_flag:1;
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ogma_uint tx_desc_ring_flag:1;
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ogma_uint running_flag:1;
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ogma_uint full_flag:1;
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ogma_uint8 desc_entry_len;
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ogma_uint16 head_idx;
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ogma_uint16 tail_idx;
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ogma_uint16 rx_num;
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ogma_uint16 tx_done_num;
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pfdep_hard_lock_t inten_reg_hard_lock;
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pfdep_soft_lock_t soft_lock;
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void *desc_ring_cpu_addr;
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pfdep_phys_addr_t desc_ring_phys_addr;
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ogma_frag_info_t *frag_info_p;
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ogma_desc_entry_priv_t *priv_data_p;
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};
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struct ogma_ctrl_s{
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ogma_ctrl_t *next_p;
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ogma_uint core_enabled_flag:1;
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ogma_uint gmac_rx_running_flag:1;
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ogma_uint gmac_tx_running_flag:1;
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ogma_uint gmac_mode_valid_flag:1;
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ogma_uint normal_desc_ring_valid:1;
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void *base_addr;
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pfdep_dev_handle_t dev_handle;
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ogma_param_t param;
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ogma_clk_ctrl_t clk_ctrl;
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ogma_uint32 rx_pkt_buf_len;
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ogma_desc_ring_t desc_ring[OGMA_DESC_RING_ID_MAX+1];
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ogma_gmac_mode_t gmac_mode;
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pfdep_hard_lock_t inten_reg_hard_lock;
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pfdep_hard_lock_t clk_ctrl_hard_lock;
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void *dummy_desc_entry_addr;
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pfdep_phys_addr_t dummy_desc_entry_phys_addr;
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ogma_uint8 phy_addr;
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#ifdef OGMA_CONFIG_REC_STAT
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/**
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* Statistics information.
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*
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* Note: Since mutual access exclusion is omitted,
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* these values might be inaccurate.
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*/
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ogma_stat_info_t stat_info;
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#endif /* OGMA_CONFIG_REC_STAT */
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};
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union ogma_desc_entry_priv_u{
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pfdep_pkt_handle_t pkt_handle;
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};
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/*****************************************************************
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*****************************************************************
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*****************************************************************/
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/**
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*
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*/
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ogma_err_t ogma_alloc_desc_ring (
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ogma_ctrl_t *ctrl_p,
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ogma_desc_ring_id_t ring_idx
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);
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/**
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*
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*/
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void ogma_free_desc_ring (
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ogma_ctrl_t *ctrl_p,
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ogma_desc_ring_t *desc_ring_p
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);
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/**
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*
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*/
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ogma_err_t ogma_setup_rx_desc_ring (
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ogma_ctrl_t *ctrl_p,
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ogma_desc_ring_t *desc_ring_p
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);
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/**
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*
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*/
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void ogma_uninit_pkt_desc_ring (
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ogma_ctrl_t *ctrl_p,
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ogma_desc_ring_t *desc_ring_p
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);
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/**
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*
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*/
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void ogma_push_clk_req (
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ogma_ctrl_t *ctrl_p,
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ogma_uint32 domain
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);
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void ogma_pop_clk_req(
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ogma_ctrl_t *ctrl_p,
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ogma_uint32 domain
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);
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ogma_err_t ogma_softreset_gmac (
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ogma_ctrl_t *ctrl_p
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);
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#ifdef OGMA_CONFIG_CHECK_CLK_SUPPLY
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#include "ogma_basic_access.h"
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/*include for ogma_read_reg*/
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static __inline void ogma_check_clk_supply (
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ogma_ctrl_t *ctrl_p,
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ogma_uint32 domain
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)
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{
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ogma_uint32 value;
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value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN);
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pfdep_assert( ( ( value & domain ) == domain) );
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}
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#else
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#define ogma_check_clk_supply( ctrl_p, domain)
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#endif /* OGMA_CONFIG_CHECK_CLK_SUPPLY */
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#endif /* OGMA_INTERNAL_H */
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