/*
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* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __MICROCHIP_PIC32_ETH_H_
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#define __MICROCHIP_PIC32_ETH_H_
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#include <mach/pic32.h>
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/* Ethernet */
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struct pic32_ectl_regs {
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struct pic32_reg_atomic con1; /* 0x00 */
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struct pic32_reg_atomic con2; /* 0x10 */
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struct pic32_reg_atomic txst; /* 0x20 */
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struct pic32_reg_atomic rxst; /* 0x30 */
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struct pic32_reg_atomic ht0; /* 0x40 */
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struct pic32_reg_atomic ht1; /* 0x50 */
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struct pic32_reg_atomic pmm0; /* 0x60 */
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struct pic32_reg_atomic pmm1; /* 0x70 */
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struct pic32_reg_atomic pmcs; /* 0x80 */
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struct pic32_reg_atomic pmo; /* 0x90 */
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struct pic32_reg_atomic rxfc; /* 0xa0 */
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struct pic32_reg_atomic rxwm; /* 0xb0 */
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struct pic32_reg_atomic ien; /* 0xc0 */
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struct pic32_reg_atomic irq; /* 0xd0 */
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struct pic32_reg_atomic stat; /* 0xe0 */
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};
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struct pic32_mii_regs {
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struct pic32_reg_atomic mcfg; /* 0x280 */
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struct pic32_reg_atomic mcmd; /* 0x290 */
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struct pic32_reg_atomic madr; /* 0x2a0 */
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struct pic32_reg_atomic mwtd; /* 0x2b0 */
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struct pic32_reg_atomic mrdd; /* 0x2c0 */
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struct pic32_reg_atomic mind; /* 0x2d0 */
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};
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struct pic32_emac_regs {
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struct pic32_reg_atomic cfg1; /* 0x200*/
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struct pic32_reg_atomic cfg2; /* 0x210*/
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struct pic32_reg_atomic ipgt; /* 0x220*/
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struct pic32_reg_atomic ipgr; /* 0x230*/
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struct pic32_reg_atomic clrt; /* 0x240*/
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struct pic32_reg_atomic maxf; /* 0x250*/
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struct pic32_reg_atomic supp; /* 0x260*/
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struct pic32_reg_atomic test; /* 0x270*/
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struct pic32_mii_regs mii; /* 0x280 - 0x2d0 */
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struct pic32_reg_atomic res1; /* 0x2e0 */
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struct pic32_reg_atomic res2; /* 0x2f0 */
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struct pic32_reg_atomic sa0; /* 0x300 */
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struct pic32_reg_atomic sa1; /* 0x310 */
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struct pic32_reg_atomic sa2; /* 0x320 */
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};
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/* ETHCON1 Reg field */
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#define ETHCON_BUFCDEC BIT(0)
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#define ETHCON_RXEN BIT(8)
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#define ETHCON_TXRTS BIT(9)
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#define ETHCON_ON BIT(15)
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/* ETHCON2 Reg field */
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#define ETHCON_RXBUFSZ 0x7f
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#define ETHCON_RXBUFSZ_SHFT 0x4
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/* ETHSTAT Reg field */
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#define ETHSTAT_BUSY BIT(7)
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#define ETHSTAT_BUFCNT 0x00ff0000
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/* ETHRXFC Register fields */
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#define ETHRXFC_BCEN BIT(0)
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#define ETHRXFC_MCEN BIT(1)
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#define ETHRXFC_UCEN BIT(3)
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#define ETHRXFC_RUNTEN BIT(4)
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#define ETHRXFC_CRCOKEN BIT(5)
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/* EMAC1CFG1 register offset */
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#define PIC32_EMAC1CFG1 0x0200
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/* EMAC1CFG1 register fields */
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#define EMAC_RXENABLE BIT(0)
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#define EMAC_RXPAUSE BIT(2)
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#define EMAC_TXPAUSE BIT(3)
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#define EMAC_SOFTRESET BIT(15)
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/* EMAC1CFG2 register fields */
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#define EMAC_FULLDUP BIT(0)
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#define EMAC_LENGTHCK BIT(1)
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#define EMAC_CRCENABLE BIT(4)
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#define EMAC_PADENABLE BIT(5)
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#define EMAC_AUTOPAD BIT(7)
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#define EMAC_EXCESS BIT(14)
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/* EMAC1IPGT register magic */
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#define FULLDUP_GAP_TIME 0x15
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#define HALFDUP_GAP_TIME 0x12
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/* EMAC1SUPP register fields */
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#define EMAC_RMII_SPD100 BIT(8)
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#define EMAC_RMII_RESET BIT(11)
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/* MII Management Configuration Register */
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#define MIIMCFG_RSTMGMT BIT(15)
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#define MIIMCFG_CLKSEL_DIV40 0x0020 /* 100Mhz / 40 */
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/* MII Management Command Register */
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#define MIIMCMD_READ BIT(0)
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#define MIIMCMD_SCAN BIT(1)
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/* MII Management Address Register */
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#define MIIMADD_REGADDR 0x1f
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#define MIIMADD_REGADDR_SHIFT 0
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#define MIIMADD_PHYADDR_SHIFT 8
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/* MII Management Indicator Register */
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#define MIIMIND_BUSY BIT(0)
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#define MIIMIND_NOTVALID BIT(2)
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#define MIIMIND_LINKFAIL BIT(3)
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/* Packet Descriptor */
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/* Received Packet Status */
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#define _RSV1_PKT_CSUM 0xffff
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#define _RSV2_CRC_ERR BIT(20)
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#define _RSV2_LEN_ERR BIT(21)
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#define _RSV2_RX_OK BIT(23)
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#define _RSV2_RX_COUNT 0xffff
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#define RSV_RX_CSUM(__rsv1) ((__rsv1) & _RSV1_PKT_CSUM)
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#define RSV_RX_COUNT(__rsv2) ((__rsv2) & _RSV2_RX_COUNT)
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#define RSV_RX_OK(__rsv2) ((__rsv2) & _RSV2_RX_OK)
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#define RSV_CRC_ERR(__rsv2) ((__rsv2) & _RSV2_CRC_ERR)
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/* Ethernet Hardware Descriptor Header bits */
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#define EDH_EOWN BIT(7)
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#define EDH_NPV BIT(8)
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#define EDH_STICKY BIT(9)
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#define _EDH_BCOUNT 0x07ff0000
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#define EDH_EOP BIT(30)
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#define EDH_SOP BIT(31)
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#define EDH_BCOUNT_SHIFT 16
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#define EDH_BCOUNT(len) ((len) << EDH_BCOUNT_SHIFT)
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/* Ethernet Hardware Descriptors
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* ref: PIC32 Family Reference Manual Table 35-7
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* This structure represents the layout of the DMA
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* memory shared between the CPU and the Ethernet
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* controller.
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*/
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/* TX/RX DMA descriptor */
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struct eth_dma_desc {
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u32 hdr; /* header */
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u32 data_buff; /* data buffer address */
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u32 stat1; /* transmit/receive packet status */
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u32 stat2; /* transmit/receive packet status */
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u32 next_ed; /* next descriptor */
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};
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#define PIC32_MDIO_NAME "PIC32_EMAC"
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int pic32_mdio_init(const char *name, ulong ioaddr);
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#endif /* __MICROCHIP_PIC32_ETH_H_*/
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