/*
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* Copyright 2010-2011 Calxeda, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <linux/compiler.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#define TX_NUM_DESC 1
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#define RX_NUM_DESC 32
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#define MAC_TIMEOUT (5*CONFIG_SYS_HZ)
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#define ETH_BUF_SZ 2048
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#define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC)
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#define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC)
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#define RXSTART 0x00000002
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#define TXSTART 0x00002000
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#define RXENABLE 0x00000004
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#define TXENABLE 0x00000008
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#define XGMAC_CONTROL_SPD 0x40000000
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#define XGMAC_CONTROL_SPD_MASK 0x60000000
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#define XGMAC_CONTROL_SARC 0x10000000
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#define XGMAC_CONTROL_SARK_MASK 0x18000000
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#define XGMAC_CONTROL_CAR 0x04000000
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#define XGMAC_CONTROL_CAR_MASK 0x06000000
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#define XGMAC_CONTROL_CAR_SHIFT 25
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#define XGMAC_CONTROL_DP 0x01000000
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#define XGMAC_CONTROL_WD 0x00800000
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#define XGMAC_CONTROL_JD 0x00400000
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#define XGMAC_CONTROL_JE 0x00100000
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#define XGMAC_CONTROL_LM 0x00001000
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#define XGMAC_CONTROL_IPC 0x00000400
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#define XGMAC_CONTROL_ACS 0x00000080
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#define XGMAC_CONTROL_DDIC 0x00000010
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#define XGMAC_CONTROL_TE 0x00000008
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#define XGMAC_CONTROL_RE 0x00000004
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#define XGMAC_DMA_BUSMODE_RESET 0x00000001
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#define XGMAC_DMA_BUSMODE_DSL 0x00000004
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#define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c
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#define XGMAC_DMA_BUSMODE_DSL_SHIFT 2
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#define XGMAC_DMA_BUSMODE_ATDS 0x00000080
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#define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00
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#define XGMAC_DMA_BUSMODE_PBL_SHIFT 8
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#define XGMAC_DMA_BUSMODE_FB 0x00010000
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#define XGMAC_DMA_BUSMODE_USP 0x00800000
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#define XGMAC_DMA_BUSMODE_8PBL 0x01000000
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#define XGMAC_DMA_BUSMODE_AAL 0x02000000
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#define XGMAC_DMA_AXIMODE_ENLPI 0x80000000
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#define XGMAC_DMA_AXIMODE_MGK 0x40000000
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#define XGMAC_DMA_AXIMODE_WROSR 0x00100000
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#define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000
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#define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20
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#define XGMAC_DMA_AXIMODE_RDOSR 0x00010000
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#define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000
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#define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16
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#define XGMAC_DMA_AXIMODE_AAL 0x00001000
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#define XGMAC_DMA_AXIMODE_BLEN256 0x00000080
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#define XGMAC_DMA_AXIMODE_BLEN128 0x00000040
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#define XGMAC_DMA_AXIMODE_BLEN64 0x00000020
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#define XGMAC_DMA_AXIMODE_BLEN32 0x00000010
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#define XGMAC_DMA_AXIMODE_BLEN16 0x00000008
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#define XGMAC_DMA_AXIMODE_BLEN8 0x00000004
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#define XGMAC_DMA_AXIMODE_BLEN4 0x00000002
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#define XGMAC_DMA_AXIMODE_UNDEF 0x00000001
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#define XGMAC_CORE_OMR_RTC_SHIFT 3
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#define XGMAC_CORE_OMR_RTC_MASK 0x00000018
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#define XGMAC_CORE_OMR_RTC 0x00000010
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#define XGMAC_CORE_OMR_RSF 0x00000020
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#define XGMAC_CORE_OMR_DT 0x00000040
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#define XGMAC_CORE_OMR_FEF 0x00000080
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#define XGMAC_CORE_OMR_EFC 0x00000100
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#define XGMAC_CORE_OMR_RFA_SHIFT 9
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#define XGMAC_CORE_OMR_RFA_MASK 0x00000E00
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#define XGMAC_CORE_OMR_RFD_SHIFT 12
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#define XGMAC_CORE_OMR_RFD_MASK 0x00007000
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#define XGMAC_CORE_OMR_TTC_SHIFT 16
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#define XGMAC_CORE_OMR_TTC_MASK 0x00030000
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#define XGMAC_CORE_OMR_TTC 0x00020000
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#define XGMAC_CORE_OMR_FTF 0x00100000
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#define XGMAC_CORE_OMR_TSF 0x00200000
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#define FIFO_MINUS_1K 0x0
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#define FIFO_MINUS_2K 0x1
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#define FIFO_MINUS_3K 0x2
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#define FIFO_MINUS_4K 0x3
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#define FIFO_MINUS_6K 0x4
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#define FIFO_MINUS_8K 0x5
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#define FIFO_MINUS_12K 0x6
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#define FIFO_MINUS_16K 0x7
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#define XGMAC_CORE_FLOW_PT_SHIFT 16
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#define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000
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#define XGMAC_CORE_FLOW_PT 0x00010000
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#define XGMAC_CORE_FLOW_DZQP 0x00000080
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#define XGMAC_CORE_FLOW_PLT_SHIFT 4
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#define XGMAC_CORE_FLOW_PLT_MASK 0x00000030
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#define XGMAC_CORE_FLOW_PLT 0x00000010
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#define XGMAC_CORE_FLOW_UP 0x00000008
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#define XGMAC_CORE_FLOW_RFE 0x00000004
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#define XGMAC_CORE_FLOW_TFE 0x00000002
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#define XGMAC_CORE_FLOW_FCB 0x00000001
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/* XGMAC Descriptor Defines */
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#define MAX_DESC_BUF_SZ (0x2000 - 8)
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#define RXDESC_EXT_STATUS 0x00000001
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#define RXDESC_CRC_ERR 0x00000002
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#define RXDESC_RX_ERR 0x00000008
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#define RXDESC_RX_WDOG 0x00000010
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#define RXDESC_FRAME_TYPE 0x00000020
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#define RXDESC_GIANT_FRAME 0x00000080
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#define RXDESC_LAST_SEG 0x00000100
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#define RXDESC_FIRST_SEG 0x00000200
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#define RXDESC_VLAN_FRAME 0x00000400
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#define RXDESC_OVERFLOW_ERR 0x00000800
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#define RXDESC_LENGTH_ERR 0x00001000
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#define RXDESC_SA_FILTER_FAIL 0x00002000
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#define RXDESC_DESCRIPTOR_ERR 0x00004000
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#define RXDESC_ERROR_SUMMARY 0x00008000
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#define RXDESC_FRAME_LEN_OFFSET 16
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#define RXDESC_FRAME_LEN_MASK 0x3fff0000
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#define RXDESC_DA_FILTER_FAIL 0x40000000
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#define RXDESC1_END_RING 0x00008000
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#define RXDESC_IP_PAYLOAD_MASK 0x00000003
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#define RXDESC_IP_PAYLOAD_UDP 0x00000001
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#define RXDESC_IP_PAYLOAD_TCP 0x00000002
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#define RXDESC_IP_PAYLOAD_ICMP 0x00000003
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#define RXDESC_IP_HEADER_ERR 0x00000008
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#define RXDESC_IP_PAYLOAD_ERR 0x00000010
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#define RXDESC_IPV4_PACKET 0x00000040
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#define RXDESC_IPV6_PACKET 0x00000080
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#define TXDESC_UNDERFLOW_ERR 0x00000001
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#define TXDESC_JABBER_TIMEOUT 0x00000002
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#define TXDESC_LOCAL_FAULT 0x00000004
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#define TXDESC_REMOTE_FAULT 0x00000008
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#define TXDESC_VLAN_FRAME 0x00000010
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#define TXDESC_FRAME_FLUSHED 0x00000020
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#define TXDESC_IP_HEADER_ERR 0x00000040
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#define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
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#define TXDESC_ERROR_SUMMARY 0x00008000
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#define TXDESC_SA_CTRL_INSERT 0x00040000
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#define TXDESC_SA_CTRL_REPLACE 0x00080000
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#define TXDESC_2ND_ADDR_CHAINED 0x00100000
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#define TXDESC_END_RING 0x00200000
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#define TXDESC_CSUM_IP 0x00400000
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#define TXDESC_CSUM_IP_PAYLD 0x00800000
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#define TXDESC_CSUM_ALL 0x00C00000
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#define TXDESC_CRC_EN_REPLACE 0x01000000
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#define TXDESC_CRC_EN_APPEND 0x02000000
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#define TXDESC_DISABLE_PAD 0x04000000
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#define TXDESC_FIRST_SEG 0x10000000
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#define TXDESC_LAST_SEG 0x20000000
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#define TXDESC_INTERRUPT 0x40000000
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#define DESC_OWN 0x80000000
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#define DESC_BUFFER1_SZ_MASK 0x00001fff
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#define DESC_BUFFER2_SZ_MASK 0x1fff0000
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#define DESC_BUFFER2_SZ_OFFSET 16
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struct xgmac_regs {
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u32 config;
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u32 framefilter;
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u32 resv_1[4];
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u32 flow_control;
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u32 vlantag;
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u32 version;
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u32 vlaninclude;
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u32 resv_2[2];
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u32 pacestretch;
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u32 vlanhash;
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u32 resv_3;
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u32 intreg;
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struct {
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u32 hi; /* 0x40 */
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u32 lo; /* 0x44 */
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} macaddr[16];
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u32 resv_4[0xd0];
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u32 core_opmode; /* 0x400 */
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u32 resv_5[0x2bf];
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u32 busmode; /* 0xf00 */
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u32 txpoll;
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u32 rxpoll;
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u32 rxdesclist;
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u32 txdesclist;
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u32 dma_status;
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u32 dma_opmode;
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u32 intenable;
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u32 resv_6[2];
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u32 axi_mode; /* 0xf28 */
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};
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struct xgmac_dma_desc {
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__le32 flags;
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__le32 buf_size;
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__le32 buf1_addr; /* Buffer 1 Address Pointer */
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__le32 buf2_addr; /* Buffer 2 Address Pointer */
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__le32 ext_status;
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__le32 res[3];
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};
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/* XGMAC Descriptor Access Helpers */
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static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
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{
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if (buf_sz > MAX_DESC_BUF_SZ)
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p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
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(buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
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else
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p->buf_size = cpu_to_le32(buf_sz);
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}
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static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
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{
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u32 len = le32_to_cpu(p->buf_size);
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return (len & DESC_BUFFER1_SZ_MASK) +
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((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
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}
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static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
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int buf_sz)
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{
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struct xgmac_dma_desc *end = p + ring_size - 1;
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memset(p, 0, sizeof(*p) * ring_size);
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for (; p <= end; p++)
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desc_set_buf_len(p, buf_sz);
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end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
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}
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static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
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{
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memset(p, 0, sizeof(*p) * ring_size);
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p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
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}
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static inline int desc_get_owner(struct xgmac_dma_desc *p)
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{
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return le32_to_cpu(p->flags) & DESC_OWN;
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}
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static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
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{
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/* Clear all fields and set the owner */
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p->flags = cpu_to_le32(DESC_OWN);
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}
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static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
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{
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u32 tmpflags = le32_to_cpu(p->flags);
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tmpflags &= TXDESC_END_RING;
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tmpflags |= flags | DESC_OWN;
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p->flags = cpu_to_le32(tmpflags);
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}
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static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
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{
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return (void *)le32_to_cpu(p->buf1_addr);
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}
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static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
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void *paddr, int len)
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{
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p->buf1_addr = cpu_to_le32(paddr);
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if (len > MAX_DESC_BUF_SZ)
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p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
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}
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static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
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void *paddr, int len)
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{
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desc_set_buf_len(p, len);
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desc_set_buf_addr(p, paddr, len);
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}
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static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
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{
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u32 data = le32_to_cpu(p->flags);
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u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
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if (data & RXDESC_FRAME_TYPE)
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len -= 4;
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return len;
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}
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struct calxeda_eth_dev {
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struct xgmac_dma_desc rx_chain[RX_NUM_DESC];
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struct xgmac_dma_desc tx_chain[TX_NUM_DESC];
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char rxbuffer[RX_BUF_SZ];
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u32 tx_currdesc;
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u32 rx_currdesc;
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struct eth_device *dev;
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} __aligned(32);
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/*
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* Initialize a descriptor ring. Calxeda XGMAC is configured to use
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* advanced descriptors.
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*/
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static void init_rx_desc(struct calxeda_eth_dev *priv)
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{
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struct xgmac_dma_desc *rxdesc = priv->rx_chain;
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struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
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void *rxbuffer = priv->rxbuffer;
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int i;
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desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
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writel((ulong)rxdesc, ®s->rxdesclist);
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for (i = 0; i < RX_NUM_DESC; i++) {
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desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
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ETH_BUF_SZ);
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desc_set_rx_owner(rxdesc + i);
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}
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}
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static void init_tx_desc(struct calxeda_eth_dev *priv)
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{
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struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
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desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
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writel((ulong)priv->tx_chain, ®s->txdesclist);
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}
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static int xgmac_reset(struct eth_device *dev)
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{
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struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
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int timeout = MAC_TIMEOUT;
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u32 value;
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value = readl(®s->config) & XGMAC_CONTROL_SPD_MASK;
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writel(XGMAC_DMA_BUSMODE_RESET, ®s->busmode);
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while ((timeout-- >= 0) &&
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(readl(®s->busmode) & XGMAC_DMA_BUSMODE_RESET))
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udelay(1);
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writel(value, ®s->config);
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return timeout;
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}
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static void xgmac_hwmacaddr(struct eth_device *dev)
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{
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struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
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u32 macaddr[2];
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memcpy(macaddr, dev->enetaddr, 6);
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writel(macaddr[1], ®s->macaddr[0].hi);
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writel(macaddr[0], ®s->macaddr[0].lo);
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}
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static int xgmac_init(struct eth_device *dev, bd_t * bis)
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{
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struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
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struct calxeda_eth_dev *priv = dev->priv;
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int value;
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if (xgmac_reset(dev) < 0)
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return -1;
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/* set the hardware MAC address */
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xgmac_hwmacaddr(dev);
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/* set the AXI bus modes */
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value = XGMAC_DMA_BUSMODE_ATDS |
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(16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) |
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XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL;
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writel(value, ®s->busmode);
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value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 |
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XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4;
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writel(value, ®s->axi_mode);
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/* set flow control parameters and store and forward mode */
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value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) |
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(FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) |
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XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF;
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writel(value, ®s->core_opmode);
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/* enable pause frames */
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value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) |
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(1 << XGMAC_CORE_FLOW_PLT_SHIFT) |
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XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE;
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writel(value, ®s->flow_control);
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/* Initialize the descriptor chains */
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init_rx_desc(priv);
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init_tx_desc(priv);
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/* must set to 0, or when started up will cause issues */
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priv->tx_currdesc = 0;
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priv->rx_currdesc = 0;
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/* set default core values */
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value = readl(®s->config);
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value &= XGMAC_CONTROL_SPD_MASK;
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value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
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XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
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/* Everything is ready enable both mac and DMA */
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value |= RXENABLE | TXENABLE;
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writel(value, ®s->config);
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value = readl(®s->dma_opmode);
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value |= RXSTART | TXSTART;
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writel(value, ®s->dma_opmode);
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return 0;
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}
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static int xgmac_tx(struct eth_device *dev, void *packet, int length)
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{
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struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
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struct calxeda_eth_dev *priv = dev->priv;
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u32 currdesc = priv->tx_currdesc;
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struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
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int timeout;
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desc_set_buf_addr_and_size(txdesc, packet, length);
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desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
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TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
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/* write poll demand */
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writel(1, ®s->txpoll);
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timeout = 1000000;
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while (desc_get_owner(txdesc)) {
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if (timeout-- < 0) {
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printf("xgmac: TX timeout\n");
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
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return 0;
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}
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static int xgmac_rx(struct eth_device *dev)
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{
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struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
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struct calxeda_eth_dev *priv = dev->priv;
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u32 currdesc = priv->rx_currdesc;
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struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
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int length = 0;
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/* check if the host has the desc */
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if (desc_get_owner(rxdesc))
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return -1; /* something bad happened */
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length = desc_get_rx_frame_len(rxdesc);
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net_process_received_packet(desc_get_buf_addr(rxdesc), length);
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/* set descriptor back to owned by XGMAC */
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desc_set_rx_owner(rxdesc);
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writel(1, ®s->rxpoll);
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priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
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return length;
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}
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static void xgmac_halt(struct eth_device *dev)
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{
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struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
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struct calxeda_eth_dev *priv = dev->priv;
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int value;
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/* Disable TX/RX */
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value = readl(®s->config);
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value &= ~(RXENABLE | TXENABLE);
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writel(value, ®s->config);
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/* Disable DMA */
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value = readl(®s->dma_opmode);
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value &= ~(RXSTART | TXSTART);
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writel(value, ®s->dma_opmode);
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/* must set to 0, or when started up will cause issues */
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priv->tx_currdesc = 0;
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priv->rx_currdesc = 0;
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}
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int calxedaxgmac_initialize(u32 id, ulong base_addr)
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{
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struct eth_device *dev;
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struct calxeda_eth_dev *priv;
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struct xgmac_regs *regs;
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u32 macaddr[2];
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regs = (struct xgmac_regs *)base_addr;
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/* check hardware version */
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if (readl(®s->version) != 0x1012)
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return -1;
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dev = malloc(sizeof(*dev));
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if (!dev)
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return 0;
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memset(dev, 0, sizeof(*dev));
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/* Structure must be aligned, because it contains the descriptors */
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priv = memalign(32, sizeof(*priv));
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if (!priv) {
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free(dev);
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return 0;
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}
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dev->iobase = (int)base_addr;
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dev->priv = priv;
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priv->dev = dev;
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sprintf(dev->name, "xgmac%d", id);
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/* The MAC address is already configured, so read it from registers. */
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macaddr[1] = readl(®s->macaddr[0].hi);
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macaddr[0] = readl(®s->macaddr[0].lo);
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memcpy(dev->enetaddr, macaddr, 6);
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dev->init = xgmac_init;
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dev->send = xgmac_tx;
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dev->recv = xgmac_rx;
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dev->halt = xgmac_halt;
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eth_register(dev);
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return 1;
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}
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