/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _IRQ_GIC_H_
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#define _IRQ_GIC_H_
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#include <asm/io.h>
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#include <irq-generic.h>
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#include <irq-platform.h>
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#include "irq-internal.h"
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/*
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* IRQ FLAG
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*/
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#define IRQ_FLG_ENABLE BIT(0)
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/*
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* IRQ-NUMBERS
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*/
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#define PLATFORM_SUSPEND_MAX_IRQ 12
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#define PLATFORM_GIC_MAX_IRQ (GIC_IRQS_NR)
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#define PLATFORM_GPIO_MAX_IRQ (GIC_IRQS_NR + GPIO_IRQS_NR)
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#define PLATFORM_MAX_IRQ (GIC_IRQS_NR + GPIO_IRQS_NR)
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/*
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* IRQ-CHIP
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*/
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struct irq_chip *arch_gic_get_irqchip(void);
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struct irq_chip *arch_gpio_get_irqchip(void);
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struct irq_chip *arch_virq_get_irqchip(void);
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/*
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* IRQ-VIRTUAL
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*/
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int bad_virq(int irq);
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void virqs_show(int pirq);
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void virq_free_handler(int irq);
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int virq_install_handler(int irq, interrupt_handler_t *handler, void *data);
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/*
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* Other
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*/
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int bad_irq(int irq);
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/*
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* IRQ-GPIO-SWITCH
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*/
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#define GPIO_BANK_MASK 0xFFFFFF00
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#define GPIO_BANK_OFFSET 8
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#define GPIO_PIN_MASK 0x000000FF
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#define GPIO_PIN_OFFSET 0
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#define EINVAL_GPIO -1
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#define PIN_BASE GIC_IRQS_NR
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struct gpio_bank {
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char *name;
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void __iomem *regbase;
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int id;
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int irq_base;
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int ngpio;
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int use_count;
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};
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#define GPIO_BANK_REGISTER(ID, GPIO_BANK_NUM) \
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{ \
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.name = __stringify(gpio##ID), \
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.regbase = (unsigned char __iomem *)GPIO##ID##_PHYS, \
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.id = ID, \
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.irq_base = PIN_BASE + (ID) * (GPIO_BANK_NUM), \
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.ngpio = GPIO_BANK_NUM, \
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.use_count = 0 \
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}
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/* gpio bank[31:8] and pin[7:0] */
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#define GPIO_BANK(gpio) ((gpio & GPIO_BANK_MASK) >> GPIO_BANK_OFFSET)
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#define GPIO_PIN(gpio) ((gpio & GPIO_PIN_MASK) >> GPIO_PIN_OFFSET)
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#define GPIO_BANK_VALID(gpio) (GPIO_BANK(gpio) < GPIO_BANK_NUM)
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#define GPIO_PIN_VALID(gpio) (GPIO_PIN(gpio) < GPIO_BANK_PINS)
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int hard_gpio_to_irq(u32 gpio);
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int irq_to_gpio(int irq);
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struct gpio_bank *gpio_id_to_bank(unsigned int id);
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struct gpio_bank *gpio_to_bank(unsigned gpio);
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void __generic_gpio_handle_irq(int irq);
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#endif /* _IRQ_GIC_H_ */
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