/*
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* Exynos PLL helper functions for clock drivers.
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* Copyright (C) 2016 Samsung Electronics
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* Thomas Abraham <thomas.ab@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <div64.h>
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#define PLL145X_MDIV_SHIFT 16
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#define PLL145X_MDIV_MASK 0x3ff
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#define PLL145X_PDIV_SHIFT 8
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#define PLL145X_PDIV_MASK 0x3f
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#define PLL145X_SDIV_SHIFT 0
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#define PLL145X_SDIV_MASK 0x7
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unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
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{
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unsigned long pll_con1 = readl(con1);
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unsigned long mdiv, sdiv, pdiv;
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uint64_t fvco = fin_freq;
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mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
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pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
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sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
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fvco *= mdiv;
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do_div(fvco, (pdiv << sdiv));
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return (unsigned long)fvco;
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}
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