/*
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* (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* Original Author Guenter Gebhardt
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* Copyright (C) 2006 Micronas GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "vct.h"
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int vct_ehci_hcd_init(u32 *hccr, u32 *hcor)
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{
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int retval;
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u32 val;
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u32 addr;
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dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
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dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
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dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
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dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON);
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dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF);
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/* Wait until (DCGU_USBPHY_STAT == 7) */
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addr = DCGU_USBPHY_STAT(DCGU_BASE);
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val = reg_read(addr);
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while (val != 7)
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val = reg_read(addr);
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dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
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dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF);
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retval = scc_reset(SCC_USB_RW, 0);
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if (retval) {
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printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval);
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return retval;
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} else {
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retval = scc_reset(SCC_CPU1_SPDMA_RW, 0);
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if (retval) {
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printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n",
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retval);
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return retval;
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}
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}
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if (!retval) {
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/*
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* For the AGU bypass, where the SCC client provides full
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* physical address
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*/
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scc_set_usb_address_generation_mode(1);
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scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
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USE_NO_FH, DMA_READ, 0);
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scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
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USE_NO_FH, DMA_WRITE, 0);
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scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
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USE_NO_FH, DMA_WRITE, 0);
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scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
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USE_NO_FH, DMA_READ, 0);
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/* Enable memory interface */
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scc_enable(SCC_USB_RW, 1);
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/* Start (start_cmd=0) DMAs */
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scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ);
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scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE);
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} else {
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printf("Cannot configure USB memory channel.\n");
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printf("USB can not access RAM. SCC configuration failed.\n");
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return retval;
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}
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/* Wait a short while */
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udelay(300000);
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reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
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/* Set EHCI structures and DATA in RAM */
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reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003);
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/* Set USBMODE to bigendian and set host mode */
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reg_write(USBH_USBMODE(USBH_BASE), 0x00000007);
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/*
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* USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for
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* 512 byte USB transfers on the bulk pipe to work properly.
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* Set USBH_BURSTSIZE to 0x00001c1c
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*/
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reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
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/* Insert access register addresses */
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*hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE);
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*hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE);
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return 0;
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}
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