function 1: modify ddr.bin file from ddrbin_param.txt.
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1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want.
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If want to keep items default, please keep these items blank.
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2) run 'ddrbin_tool' with argument 1: chip_name, argument 2: ddrbin_param.txt, argument 3: ddr bin file.
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like: ./ddrbin_tool px30 ddrbin_param.txt px30_ddr_333MHz_v1.13.bin
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function 2: get ddr.bin file config to gen_param.txt file
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If want to get ddrbin file config, please run like that:
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./ddrbin_tool px30 -g gen_param.txt px30_ddr_333MHz_v1.15.bin
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The config will show in gen_param.txt.
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The detail information as following:
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* support ddrbin version
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The 'X' means not support change those parameters by tool.
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT | ddr2/3/4, lp2/3 Vref |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| PX30/RK3326 | V1.11 | X | V1.16 | V1.12 | V1.15 | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3288 | V1.11 | X | X | V1.11 | X | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3308S | V2.05 | V2.05 | V2.05 | V2.05 | V2.05 | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3399PRO NPU | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | V1.19 |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3588 | V1.00 | V1.00 | X | V1.00 | V1.00 | V1.00 | X | X | X |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3528 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.08 |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| RK3562 | X | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.05 |
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+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+
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| function | platform and ddrbin version |
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| ------------------------------------- | ------------------------------------------ |
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| first scan channel/channel mask | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 |
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| stride type | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 |
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| ext_temp_ref | RK356x V1.16 |
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| link_ecc_en | Null |
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| per_bank_ref_en | RK3588 V1.09 |
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| derate_en | RK3588 V1.09 |
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| auto_precharge_en | Null |
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| res_space_remap_portion | RK3588 V1.09 |
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| res_space_remap_all | RK3588 V1.09 |
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| rd_vref_scan_en | RK3588 V1.08 |
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| wr_vref_scan_en | RK3588 V1.08 |
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| eye_2d_scan_en | RK3588 V1.08 |
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| ch/bank/rank_mask | RK3588 V1.00 |
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| pstore base_addr/buf_size | RK3588 V1.09 |
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| uboot/atf/optee/spl/tpl log en | RK3588 V1.09 |
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| boot_fsp | RK3588 V1.09 |
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| pageclose | RK3588 V1.10 |
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| first_init_dram_type/dfs_disable | RK3588 V1.11 |
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* UART info
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uart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart.
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uart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2),
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or 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c).
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uart baudrate: uart baudrate should be 115200 or 1500000.
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* disable print training information
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dis_train_print: 1: will disabled print training information; 0: will enable print training information.
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* recycle registers space(remap register space to DDR)
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res_space_remap_portion
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1: will remap the part of registers to DDR memory space(will not larger than 4GB).
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It is PCIE and some reserved space in RK3588, and the PCIE can not be used when set to 1.
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res_space_remap_all
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1: will wrap all registers space(include res_space_remap_portion enable space) to DDR memory space. This space would be place in larger than 4GB.
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The PCIE can be used when set to 1 in RK3588.
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* DDR eye scanning
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1) eye_2d_scan_en: 1: will enable 2D eye scanning for debug purpose, vref and skew eye scanning.
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2) wr_vref_scan_en: 1: enable vref scan and use scanning result for write.
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3) rd_vref_scan_en: 1: enable vref scan and use scanning result for read.
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* DDR auto precharge
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auto_precharge_en: 1: will enable the DDR auto precharge.
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* DDR refresh derate
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derate_en: 1: will enable derate function of the LP2/LP3/LP4/LP4X/LP5.
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The high temperature will issue more refresh command and the low temperature will less.
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* DDR per bank refresh
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per_bank_ref_en: 1: will enable per bank refresh
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* link ECC enable
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link_ecc_en: 1: read/write link ecc enable.
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* Extended temperature refresh
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ext_temp_ref:
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0: ref1x for normal chip, 2x for 3568M/3568J
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1: fix 2x ref for all chip
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2: fix 4x ref for all chip
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3: fix 1x ref for all chip
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Note: If derate-enabled DDR are configured with derate_en=1, the ext_temp_ref configuration does not take effect.
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* pstore_base_addr pstore_buf_size
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The pstore buffer base address: pstore_base_addr << 16, 64kB align.
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The pstore buffer size: pstore_buf_size * 4KB.
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It is define the addr and size to save ddrbin log for last log.
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* uboot_log_en
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1: enable uboot log.
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0: disable uboot log.
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* atf_log_en
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1: enable atf log.
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0: disable atf log.
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* optee_log_en
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1: enable optee log.
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0: disable optee log.
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* spl_log_en
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1: enable spl log.
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0: disable spl log.
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* tpl_log_en
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1: enable tpl log.
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0: disable tpl log.
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* pageclose
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1: enable pageclose.
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0: disable pageclose.
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* boot_fsp
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To choose the which DDR freq to boot system. 0 means fsp0_freq, 1 means fsp1_freq, 2 means fsp2_freq, 3 means fsp3_freq, the default is 0.
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* first_init_dram_type
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The define first init dram type to saving initial time.
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|----------------------------|-----------------|
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| first_init_dram_type value | DDR type |
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| 0 | DDR4 |
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| 2 | DDR2 |
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| 3 | DDR3 |
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| 5 | LPDDR2 |
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| 6 | LPDDR3 |
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| 7 | LPDDR4 |
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| 8 | LPDDR4X |
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| 9 | LPDDR5 |
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| 10 | DDR5 |
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|----------------------------|-----------------|
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* dfs_disable
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1: disbale ddr freq switch function
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0: enable ddr freq switch function
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Note:
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The starting frequency is fixed to f0 frequency after turning off the frequency scaling.
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If the DDR frequency needs to be modified, ddrx_f0_freq/fsp0_freq should be modified.
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* DDR (final) freq(also called ddrx_f0_freq_mhz/fsp0_freq)
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For RK3588, the boot_fsp used to choose which ddrx_fx_freq_mhz/fspx_freq to boot system, default is ddrx_f0_freq_mhz/fsp0_freq.
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For the others platform, it is the final freq to boot system.
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ddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz.
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lp2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz.
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ddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz.
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lp3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz.
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ddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz.
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lp4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz.
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lp4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz.
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lp5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz.
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* support ddr frequency:
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The 'X' as follows means not support change frequencies by tool.
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+---------------+-----------------------------------------------------------------+
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| platform | support frequencies(MHZ) |
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+---------------+-----------------------------------------------------------------+
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| RK1108 | DDR2: 400; LP2: <= 533; DDR3: <= 800 |
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+---------------+-----------------------------------------------------------------+
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| PX30/RK3326 | X |
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+---------------+-----------------------------------------------------------------+
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| RK1808 | 333,400,533,666,786,933 |
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+---------------+-----------------------------------------------------------------+
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| RK322x | DDR2/LP2: <= 533; others: <= 800 |
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+---------------+-----------------------------------------------------------------+
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| RK322xh | X |
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+---------------+-----------------------------------------------------------------+
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| RK3288 | X |
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+---------------+-----------------------------------------------------------------+
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| RK3308/RK3308S| DDR2/LP2: 393,451; DDR3: 393,451,589 |
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+---------------+-----------------------------------------------------------------+
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| RK3368 | DDR3: <= 800; LP3: <= 666 |
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+---------------+-----------------------------------------------------------------+
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| RK3328 | X |
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+---------------+-----------------------------------------------------------------+
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| RK3399 | X |
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+---------------+-----------------------------------------------------------------+
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| RK3399PRO NPU | 333,400,533,666,786,933 |
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+---------------+-----------------------------------------------------------------+
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| RV1126/RV1109 | 328,396,528,664,784,924,1056 |
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+---------------+-----------------------------------------------------------------+
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| RK3566 | 324,396,528,630,780,920,1056 |
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+---------------+-----------------------------------------------------------------+
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| RK3568 | DDR3/LP3: 324,396,528,630,780,920,1056 |
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| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184,1332,1560 |
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+---------------+-----------------------------------------------------------------+
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| RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] |
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+---------------+-----------------------------------------------------------------+
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| RK3528 | DDR3/LP3/LP4/LP4X: 324,396,528,630,780,920,1056 |
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| | DDR4: 324,396,528,630,780,920,1056,1184 |
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+---------------+-----------------------------------------------------------------+
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| RK3562 | DDR3/LP3: [324MHz - 1056MHz]; LP4/LP4X/DDR4: [324MHz - 1392MHz] |
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+---------------+-----------------------------------------------------------------+
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* DDR frequencies(add more)
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ddr2_f1_freq_mhz: ddr2 frequency fsp 1, unit:MHz.
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ddr2_f2_freq_mhz: ddr2 frequency fsp 2, unit:MHz.
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ddr2_f3_freq_mhz: ddr2 frequency fsp 3, unit:MHz.
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ddr2_f4_freq_mhz: ddr2 frequency fsp 4, unit:MHz.
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ddr2_f5_freq_mhz: ddr2 frequency fsp 5, unit:MHz.
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...
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The ddrx_f0_freq_mhz(the fsp0 frequency) is named ddrx_freq.
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ddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used.
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The program will initialize dram by following order.
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for example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq.
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And the final frequency is ddr4_freq to boot system.
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The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies.
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So it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'.
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Such as: ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq)
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For example:
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...
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ddr4_freq=1560
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...
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ddr4_f1_freq_mhz=324
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ddr4_f2_freq_mhz=528
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ddr4_f3_freq_mhz=780
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...
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Note: The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies.
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* SR PD idle
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sr_idle: auto self-refresh mode delay time.
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pd_idle: auto power-down mode delay time.
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* DDR 2T
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ddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T.
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* PLL ssmod
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These parameters are about Spread Spectrum Modulator(ssmod) for PLL.
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ssmod_downspread: ssmod work mode.
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2'b00: center spread. (Suggest to use center spread for better clock jitter)
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2'b01: down spread.
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2'b10: up spread.(Please refer to the datasheet for support information)
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2'b11: reserved
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ssmod_div: Divider required to set the modulation frequency.
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RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5.
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ssmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f.
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The larger the ssmod_spread value, the smaller of EMI, the worse of clk jitter.
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Suggest to use ssmod_spread = 5, which means the center spread is +/-0.5%.
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Please refer to "Rockchip_Developer_Guide_Pll_Ssmod_Clock_CN" for more information.
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* driver strength
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phy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm.
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phy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm.
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phy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm.
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ddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm.
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phy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm.
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phy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm.
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phy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm.
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ddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm.
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The phy side driver strength support value as follows:
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+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+
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| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 |
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+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+
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| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | |
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| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | |
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| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | X |
|
| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | |
|
| | 20 | 21 | | 25,24,23,22 | | | |
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+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+
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| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | |
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| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | |
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| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X |
|
| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| |
|
| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| |
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| | | | | | 28 | 23 | |
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+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+
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| RK3588 | X | X | X | 240,120,80,60, | follow LP4 | follow LP4 | follow LP4 |
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| | | | | 48,40,34,30 | | | |
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+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+
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| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 585,297,202, | 585,297,202, | |
|
| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 150,122,103,90,| |
|
| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43,| follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X |
|
| | 38,36,34,33,31,30,| 39,37,35,34,32,31,| | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| |
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| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| |
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| | | | | | 30 | 30 | |
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+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+
|
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The DRAM side driver strength support value as follows:
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+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+
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| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | LP5 |
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+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+
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| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | follow LP4 |
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+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+
|
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* ODT
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phy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm.
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ddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm.
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phy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable
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phy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable
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phy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz.
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ddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz.
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The phy side ODT support value as follows:
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The ODT "0" means disabled ODT.
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+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+
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| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 |
|
+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+
|
| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | |
|
| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | |
|
| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | X |
|
| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | |
|
| | 28,27,25 | 27 | | 29,27 | | | |
|
+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+
|
| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | |
|
| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | |
|
| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X |
|
| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| |
|
| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| |
|
| | | | | | 28 | 23 | |
|
+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+
|
| RK3588 | X | X | X | 0,240,120,80, | follow LP4 | follow LP4 | follow LP4 |
|
| | | | | 60,48,40,34,30 | | | |
|
+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+
|
| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 585,297,202, | 585,297,202, | |
|
| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 150,122,103,90,| |
|
| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43, | follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X |
|
| | 38,36,34,33,31,30,| 39,37,35,34,32,31, | | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| |
|
| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| |
|
| | | | | | 30 | 30 | |
|
+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+
|
The DRAM side ODT support value as follows:
|
+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+
|
| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | LP5 |
|
+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+
|
| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | follow LP4 |
|
+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+
|
|
* slew rate
|
|
phy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on.
|
phy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on.
|
phy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on.
|
phy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off.
|
phy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off.
|
phy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off.
|
|
The max value is 0x1f, the min is 0x0.
|
|
* byte map
|
|
ddr*_bytes_map: The bytes remap in PHY.
|
|
* dq remap
|
|
lp*_dq*_*_map: The dq remap in PHY.
|
ddr*_cs*_dq*_dq*_map: The dq remap in PHY.
|
|
* lp4/lp4x more information
|
|
lp4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz.
|
|
* vref
|
|
phy_ddr*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand.
|
ddr*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand.
|
ddr*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand.
|
phy_ddr*_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand.
|
ddr*_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand.
|
ddr*_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand.
|
|
For DDR2/3/4 and LPDDR2/3, if the configuration value is "0", Vref is automatically calculated by the code.
|
|
* hash info
|
ch/bank/rank_mask*: is used to DDR address hash mask.
|
|
* modify skew info
|
|
ddr*_skew_freq_mhz: Used to specify the frequency of skew.
|
|
ddr*_skew: The skew value of dram type are need to modify. If need to modify skew, you must check with the hardware engineer.
|
|
The support platform:
|
|---------------------------|--------------------|--------------------------------------------|
|
| platform | ddrbin version | calculate one step delay(ps) |
|
| RK3528 | V1.06 | 1000000 / ddr*_skew_freq_mhz / 128 |
|
|---------------------------|--------------------|--------------------------------------------|
|
|
For RK3528, the skew one step is 7.398ps when ddr*_skew_freq_mhz is 1056.
|
|
Before modify skew, it is recommended to read every CA skew from the bin file and then adjust the CA skew which want to change.
|
