/*
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* Copyright (C) 2019 Spreadtrum Communications Inc.
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*
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* Authors : xiaodong.bi
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "wcn_swd_dp.h"
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#ifdef CONFIG_WCN_PCIE
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static void swd_ext_sel(bool enable)
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{
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u32 *reg = (u32 *)(pcie_bar_vmem(4) + 0x1c);
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u32 *ahb_ctl = (u32 *)(pcie_bar_vmem(0) + 0x001303e8);/* dis sec */
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*ahb_ctl = 0x73e;
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if (enable)
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*reg |= (BIT(7) | BIT(6) | BIT(5));
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else
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*reg &= ~(BIT(7) | BIT(6) | BIT(5));
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}
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static void swclk_clr(void)
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{
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u32 *reg = (u32 *)(pcie_bar_vmem(4) + 0x1c);
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*reg &= ~BIT(6);
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}
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static void swclk_set(void)
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{
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u32 *reg = (u32 *)(pcie_bar_vmem(4) + 0x1c);
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*reg |= BIT(6);
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}
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static void sw_dio_out(u32 value)
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{
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u32 *reg = (u32 *)(pcie_bar_vmem(4) + 0x1c);
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if (value & BIT(0))
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*reg |= BIT(5);
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else
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*reg &= ~BIT(5);
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}
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static u32 sw_dio_in(void)
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{
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u32 *reg = (u32 *)(pcie_bar_vmem(4) + 0xc);
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u32 bit;
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bit = (*reg & BIT(7)) >> 7;
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return bit;
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}
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#elif defined CONFIG_WCN_USB
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static void swd_ext_sel(bool enable)
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{
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}
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static void swclk_clr(void)
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{
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}
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static void swclk_set(void)
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{
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}
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static void sw_dio_out(u32 value)
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{
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}
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static u32 sw_dio_in(void)
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{
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return 0;
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}
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#else
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static void swd_ext_sel(bool enable)
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{
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unsigned char reg;
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sdiohal_aon_readb(DAP_ADDR+0x0E, ®);
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pr_info("reg value is:0x%x\n", reg);
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if (enable)
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reg |= (BIT(7) | BIT(6) | BIT(5));
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else
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reg &= ~(BIT(7) | BIT(6) | BIT(5));
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sdiohal_aon_writeb(DAP_ADDR+0x0E, reg);
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sdiohal_aon_readb(DAP_ADDR+0x0E, ®);
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pr_info("reg value is:0x%x\n", reg);
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}
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static void swclk_clr(void)
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{
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unsigned char reg;
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sdiohal_aon_readb(DAP_ADDR+0x0e, ®);
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reg &= ~BIT(6);
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sdiohal_aon_writeb(DAP_ADDR+0x0E, reg);
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}
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static void swclk_set(void)
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{
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unsigned char reg;
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sdiohal_aon_readb(DAP_ADDR+0x0E, ®);
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reg |= BIT(6);
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sdiohal_aon_writeb(DAP_ADDR+0x0E, reg);
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}
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static void sw_dio_out(u32 value)
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{
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unsigned char reg;
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sdiohal_aon_readb(DAP_ADDR+0x0E, ®);
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if (value & BIT(0))
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reg |= BIT(5);
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else
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reg &= ~BIT(5);
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sdiohal_aon_writeb(DAP_ADDR+0x0E, reg);
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}
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static u32 sw_dio_in(void)
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{
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unsigned char reg;
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u32 bit;
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sdiohal_aon_readb(DAP_ACK_ADDR, ®);
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bit = (reg & BIT(7)) >> 7;
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return bit;
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}
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#endif
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static void swd_clk_cycle(void)
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{
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swclk_set();
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ndelay(100);
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swclk_clr();
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ndelay(100);
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}
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static void swd_write_bit(u32 bit)
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{
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swclk_set();
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sw_dio_out(bit);
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ndelay(100);
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swclk_clr();
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ndelay(100);
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}
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static u32 swd_read_bit(void)
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{
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u32 bit;
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swclk_set();
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ndelay(100);
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bit = sw_dio_in();
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swclk_clr();
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ndelay(100);
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return bit;
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}
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static void swd_insert_cycles(u32 n)
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{
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u32 i;
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for (i = 0; i < n; i++)
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swd_clk_cycle();
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}
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u32 swd_transfer(u8 cmd, u32 *data)
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{
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u32 ack = 0;
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u32 bit;
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u32 val;
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u32 parity;
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u32 n;
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parity = 0;
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/* Start Bit */
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swd_write_bit(1);
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bit = ((cmd >> 0) & BIT(0));
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/* APnDP Bit */
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swd_write_bit(bit);
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parity += bit;
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bit = ((cmd >> 1) & BIT(0));
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/* RnW Bit */
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swd_write_bit(bit);
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parity += bit;
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bit = ((cmd >> 2) & BIT(0));
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/* A2 Bit */
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swd_write_bit(bit);
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parity += bit;
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bit = ((cmd >> 3) & BIT(0));
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/* A3 Bit */
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swd_write_bit(bit);
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parity += bit;
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/* Parity Bit */
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swd_write_bit(parity & BIT(0));
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/* Stop Bit */
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swd_write_bit(0);
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/* Park Bit */
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swd_write_bit(1);
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/* Turnaround */
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swd_insert_cycles(1);
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/* Acknowledge response */
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bit = swd_read_bit();
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ack |= bit << 0;
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bit = swd_read_bit();
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ack |= bit << 1;
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bit = swd_read_bit();
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ack |= bit << 2;
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if (ack == DAP_TRANSFER_OK) {
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/* Data transfer */
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if (cmd & DAP_TRANSFER_RnW) {
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val = 0;
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parity = 0;
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/* Read DATA[0:31] */
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for (n = 0; n < 32; n++) {
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bit = swd_read_bit();
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parity += bit;
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val |= (bit << n);
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}
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/* Read Parity */
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bit = swd_read_bit();
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if ((parity ^ bit) & 1)
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ack = DAP_TRANSFER_ERROR;
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if (data)
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*data = val;
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/* Turnaround */
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swd_insert_cycles(1);
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} else {
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/* Turnaround */
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swd_insert_cycles(1);
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sw_dio_out(0);
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val = *data;
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parity = 0;
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/* Write WDATA[0:31] */
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for (n = 0; n < 32; n++) {
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bit = val & BIT(0);
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swd_write_bit(bit);
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parity += bit;
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val >>= 1;
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}
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/* Write Parity Bit */
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swd_write_bit(parity & BIT(0));
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/* Turnaround */
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swd_insert_cycles(1);
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}
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/* Idle cycles >= 8 */
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sw_dio_out(0);
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swd_insert_cycles(8);
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return ack;
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}
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if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) {
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if ((cmd & DAP_TRANSFER_RnW) != 0)
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swd_insert_cycles(32+1);
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else {
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/* Turnaround */
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swd_insert_cycles(1);
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if ((cmd & DAP_TRANSFER_RnW) == 0)
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swd_insert_cycles(32 + 1);
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}
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/* Idle cycles >= 8 */
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sw_dio_out(0);
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swd_insert_cycles(8);
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return ack;
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}
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/* Turnaround */
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swd_insert_cycles(1);
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swd_insert_cycles(32+1);
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/* Idle cycles >= 8 */
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sw_dio_out(0);
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swd_insert_cycles(8);
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return ack;
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}
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static void swd_send_nbytes(u8 *buf, int nbytes)
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{
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u8 i, j;
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u8 dat;
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for (i = 0; i < nbytes; i++) {
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dat = buf[i];
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for (j = 0; j < 8; j++) {
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if ((dat & 0x80) == 0x80)
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swd_write_bit(1);
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else
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swd_write_bit(0);
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dat <<= 1;
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}
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}
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}
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static u32 swd_dap_read(u8 reg, u32 *data)
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{
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u32 ack;
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reg &= ~DAP_TRANSFER_APnDP;
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reg |= DAP_TRANSFER_RnW;
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ack = swd_transfer(reg, data);
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return ack;
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}
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static u32 swd_dap_write(u8 reg, u32 *data)
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{
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u32 ack;
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reg &= ~(DAP_TRANSFER_APnDP | DAP_TRANSFER_RnW);
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ack = swd_transfer(reg, data);
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return ack;
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}
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static u32 swd_ap_read(u8 reg, u32 *data)
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{
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u32 ack;
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reg |= DAP_TRANSFER_APnDP | DAP_TRANSFER_RnW;
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ack = swd_transfer(reg, data);
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return ack;
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}
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static u32 swd_ap_write(u32 reg, u32 *data)
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{
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u32 ack;
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reg &= ~(DAP_TRANSFER_RnW);
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reg |= DAP_TRANSFER_APnDP;
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ack = swd_transfer(reg, data);
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return ack;
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}
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static u32 swd_memap_read(u32 addr, u32 *data)
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{
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u8 reg;
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u32 ack;
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reg = DAP_TRANSFER_A2;
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ack = swd_ap_write(reg, &addr);
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reg = DAP_TRANSFER_A2 | DAP_TRANSFER_A3;
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ack = swd_ap_read(reg, data);
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ack = swd_ap_read(reg, data);
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return ack;
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}
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static u32 swd_memap_write(u32 addr, u32 *data)
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{
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u8 reg;
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u32 ack;
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reg = DAP_TRANSFER_A2;
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ack = swd_ap_write(reg, &addr);
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reg = DAP_TRANSFER_A2 | DAP_TRANSFER_A3;
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ack = swd_ap_write(reg, data);
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return ack;
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}
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static void swd_read_arm_core(void)
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{
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u32 value;
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u32 index;
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u32 addr;
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static const char *core_reg_name[19] = {
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"R0 ", "R1 ", "R2 ", "R3 ", "R4 ", "R5 ", "R6 ", "R7 ", "R8 ",
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"R9 ", "R10", "R11", "R12", "R13", "R14", "R15", "PSR", "MSP",
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"PSP",
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};
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/* reg arm reg */
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for (index = 0; index < 19; index++) {
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addr = 0xe000edf4;
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swd_memap_write(addr, &index);
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addr = 0xe000edf8;
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swd_memap_read(addr, &value);
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pr_info("%s %s:0x%x\n", __func__, core_reg_name[index], value);
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}
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}
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/* MSB first */
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u8 swd_wakeup_seq[16] = {
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0x49, 0xCF, 0x90, 0x46,
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0xA9, 0xB4, 0xA1, 0x61,
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0x97, 0xF5, 0xBB, 0xC7,
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0x45, 0x70, 0x3D, 0x98,
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};
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/* LSB first */
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u8 swd_wakeup_seq2[16] = {
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0x19, 0xBC, 0x0E, 0xA2,
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0xE3, 0xDD, 0xAF, 0xE9,
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0x86, 0x85, 0x2D, 0x95,
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0x62, 0x09, 0xF3, 0x92,
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};
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u8 swd_to_ds_seq[2] = {
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0x3d, 0xc7,
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};
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static void swd_dormant_to_wake(void)
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{
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u8 data;
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/* Send at least eight SWCLKTCK cycles with SWDIOTMS HIGH */
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sw_dio_out(1);
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swd_insert_cycles(8);
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/* 128 bit Selection Alert sequence */
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swd_send_nbytes(swd_wakeup_seq, 16);
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/* four SWCLKTCK cycles with SWDIOTMS LOW */
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sw_dio_out(0);
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swd_insert_cycles(4);
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/* Send the activation code */
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data = 0x58;
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swd_send_nbytes(&data, 1);
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swd_insert_cycles(1);
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sw_dio_out(0);
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}
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static void swd_wake_to_dormant(void)
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{
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/* Send at least eight SWCLKTCK cycles with SWDIOTMS HIGH */
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sw_dio_out(1);
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swd_insert_cycles(8);
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/* 16-bit SWD-to-DS select sequence */
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swd_send_nbytes(swd_to_ds_seq, 2);
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swd_insert_cycles(1);
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}
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static void switch_jtag_to_swd(void)
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{
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u8 data[2];
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/* Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH */
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sw_dio_out(1);
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swd_insert_cycles(50);
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/* send the 16-bit JTAG-to-SWD select sequence */
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data[0] = 0x79;
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data[1] = 0xe7;
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swd_send_nbytes(data, 2);
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/* Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH */
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swd_insert_cycles(50);
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sw_dio_out(0);
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}
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static void swd_line_reset(void)
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{
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/* Complete SWD reset sequence
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*(50 cycles high followed by 2 or more idle cycles)
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*/
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sw_dio_out(1);
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swd_insert_cycles(50);
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sw_dio_out(0);
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swd_insert_cycles(2);
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}
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static void swd_read_dpidr(void)
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{
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u32 ack, data = 0;
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/* the dp idr is 0x0be12477*/
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ack = swd_dap_read(DP_IDCODE, &data);
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pr_info("%s idcode:0x%x\n", __func__, data);
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}
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static void swd_read_apidr(void)
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{
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u32 ack, data = 0;
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data = (0xf << 4);
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ack = swd_dap_write(DP_SELECT, &data);
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/* the dp idr is 0x14770015*/
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ack = swd_ap_read(AP_IDCODE, &data);
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ack = swd_ap_read(AP_IDCODE, &data);
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pr_info("%s idcode:0x%x\n", __func__, data);
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data = (0x0 << 4);
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ack = swd_dap_write(DP_SELECT, &data);
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}
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u32 swd_sel_target(u8 cmd, u32 *data)
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{
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u32 bit, parity;
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u32 n, val;
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sw_dio_out(1);
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swd_insert_cycles(50);
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sw_dio_out(0);
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swd_insert_cycles(2);
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parity = 0;
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/* Start Bit */
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swd_write_bit(1);
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bit = ((cmd >> 0) & BIT(0));
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/* APnDP Bit */
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swd_write_bit(bit);
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parity += bit;
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bit = ((cmd >> 1) & BIT(0));
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/* RnW Bit */
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swd_write_bit(bit);
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parity += bit;
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bit = ((cmd >> 2) & BIT(0));
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/* A2 Bit */
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swd_write_bit(bit);
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parity += bit;
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bit = ((cmd >> 3) & BIT(0));
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/* A3 Bit */
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swd_write_bit(bit);
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parity += bit;
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/* Parity Bit */
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swd_write_bit(parity & BIT(0));
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/* Stop Bit */
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swd_write_bit(0);
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/* Park Bit */
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swd_write_bit(1);
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/* Turnaround */
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swd_insert_cycles(5);
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val = *data;
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parity = 0;
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/* Write WDATA[0:31] */
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for (n = 0; n < 32; n++) {
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bit = (val & BIT(0));
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swd_write_bit(bit);
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parity += bit;
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val >>= 1;
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}
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/* Write Parity Bit */
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swd_write_bit(parity & BIT(0));
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sw_dio_out(0);
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swd_insert_cycles(3);
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return 0;
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}
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static void btwf_sys_dap_sel(void)
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{
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u32 data = 0;
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swd_line_reset();
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data = TARGETSEL_CP;
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swd_sel_target(DP_TARGETSEL, &data);
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swd_read_dpidr();
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}
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static int swd_power_up(void)
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{
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u32 data;
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pr_info("%s entry\n", __func__);
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data = 0x50000000;
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swd_dap_write(DP_CTRL_STAT, &data);
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swd_dap_read(DP_CTRL_STAT, &data);
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pr_info("%s read ctrl stat:0x%x\n", __func__, data);
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return 0;
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}
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static void swd_device_en(void)
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{
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u32 data = 0;
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swd_ap_read(AP_CTRL, &data);
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swd_ap_read(AP_CTRL, &data);
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data = (data & 0xffffff88) | BIT(1) | BIT(6);
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swd_ap_write(AP_STAT, &data);
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}
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/* Debug Exception and Monitor Control Register */
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/* (0xe000edfC) = 0x010007f1 */
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void swd_set_debug_mode(void)
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{
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int ret;
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int addr;
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unsigned int reg_val;
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reg_val = 0x010007f1;
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addr = 0xe000edfC;
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ret = swd_memap_write(addr, ®_val);
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if (ret < 0) {
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pr_info("%s error:%d\n", __func__, ret);
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return;
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}
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/*test */
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ret = swd_memap_read(addr, ®_val);
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if (ret < 0) {
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pr_info("%s error:%d\n", __func__, ret);
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return;
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}
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pr_info("%s arm debug reg value is 0x%x:\n", __func__, reg_val);
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}
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/*
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* Debug Halting Control status Register
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* (0xe000edf0) = 0xa05f0003
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*/
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void swd_hold_btwf_core(void)
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{
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int ret;
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int addr;
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unsigned int reg_val;
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addr = 0xe000edf0;
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reg_val = 0xa05f0003;
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ret = swd_memap_write(addr, ®_val);
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if (ret < 0) {
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pr_info("%s error:%d\n", __func__, ret);
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return;
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}
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/*test */
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ret = swd_memap_read(addr, ®_val);
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if (ret < 0) {
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pr_info("%s error:%d\n", __func__, ret);
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return;
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}
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pr_info("%s arm hold btwf reg value is 0x%x:\n", __func__, reg_val);
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}
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int swd_dump_arm_reg(void)
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{
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pr_info("%s entry\n", __func__);
|
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swd_ext_sel(true);
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swd_line_reset();
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switch_jtag_to_swd();
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swd_dormant_to_wake();
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btwf_sys_dap_sel();
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swd_power_up();
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swd_read_apidr();
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swd_device_en();
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swd_hold_btwf_core();
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swd_set_debug_mode();
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swd_read_arm_core();
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/* release swd */
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swd_wake_to_dormant();
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swd_ext_sel(false);
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pr_info("%s end\n", __func__);
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return 0;
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}
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