/*
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* Copyright (C) 2016-2018 Spreadtrum Communications Inc.
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <wcn_bus.h>
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#include "edma_engine.h"
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#include "mchn.h"
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static struct mchn_info_t g_mchn;
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struct mchn_info_t *mchn_info(void)
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{
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return &g_mchn;
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}
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struct mchn_ops_t *mchn_ops(int channel)
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{
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return g_mchn.ops[channel];
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}
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int mbuf_link_alloc(int chn, struct mbuf_t **head, struct mbuf_t **tail,
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int *num)
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{
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int i;
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struct mbuf_t *cur, *head__, *tail__ = NULL;
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struct mchn_info_t *mchn = mchn_info();
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struct buffer_pool *pool = &(mchn->chn_public[chn].pool);
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PCIE_INFO("pool=%p, chn=%d, free=%d\n", pool, chn, pool->free);
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spin_lock_irqsave(&(pool->lock), pool->irq_flags);
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if ((*num <= 0) || (pool->free <= 0)) {
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PCIE_ERR("[+]%s err, num %d, free %d)\n",
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__func__, *num, pool->free);
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*num = 0;
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*head = *tail = NULL;
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spin_unlock_irqrestore(&(pool->lock), pool->irq_flags);
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return -1;
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}
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if (*num > pool->free)
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*num = pool->free;
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for (i = 0, cur = head__ = pool->head; i < *num; i++) {
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if (i == (*num - 1))
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tail__ = cur;
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cur = cur->next;
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}
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*head = head__;
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tail__->next = NULL;
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*tail = tail__;
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pool->free -= *num;
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pool->head = cur;
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spin_unlock_irqrestore(&(pool->lock), pool->irq_flags);
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return 0;
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}
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EXPORT_SYMBOL(mbuf_link_alloc);
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int mbuf_link_free(int chn, struct mbuf_t *head, struct mbuf_t *tail, int num)
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{
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struct mchn_info_t *mchn = mchn_info();
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struct buffer_pool *pool = &(mchn->chn_public[chn].pool);
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if ((head == NULL) || (tail == NULL) || (num == 0) ||
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(tail->next != 0)) {
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PCIE_ERR("%s@%d(%d, 0x%p, 0x%p, %d)err\n",
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__func__, __LINE__, chn, head, tail, num);
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return -1;
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}
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spin_lock_irqsave(&(pool->lock), pool->irq_flags);
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tail->next = pool->head;
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pool->head = head;
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pool->free += num;
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spin_unlock_irqrestore(&(pool->lock), pool->irq_flags);
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return 0;
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}
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EXPORT_SYMBOL(mbuf_link_free);
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int mbuf_pool_init(struct buffer_pool *pool, int size, int payload)
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{
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int i;
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struct mbuf_t *mbuf, *next;
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pool->size = size;
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pool->payload = payload;
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spin_lock_init(&(pool->lock));
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pool->mem = kmalloc((sizeof(struct mbuf_t) + payload) * size,
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GFP_KERNEL);
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PCIE_INFO("mbuf_pool->mem:0x%lx\n",
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(unsigned long)virt_to_phys(pool->mem));
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memset(pool->mem, 0x00, (sizeof(struct mbuf_t) + payload) * size);
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pool->head = (struct mbuf_t *) (pool->mem);
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for (i = 0, mbuf = (struct mbuf_t *) (pool->head);
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i < (size - 1); i++) {
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mbuf->seq = i;
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PCIE_INFO("%s mbuf[%d]:{0x%lx, 0x%lx}\n", __func__, i,
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(unsigned long)mbuf,
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(unsigned long)virt_to_phys(mbuf));
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next = (struct mbuf_t *) ((char *)mbuf +
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sizeof(struct mbuf_t) + payload);
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mbuf->buf = (char *)mbuf + sizeof(struct mbuf_t);
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mbuf->len = payload;
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mbuf->next = next;
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mbuf = next;
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}
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PCIE_INFO("%s mbuf[%d]:{0x%lx, 0x%lx}\n", __func__, i,
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(unsigned long)mbuf,
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(unsigned long)virt_to_phys(mbuf));
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mbuf->seq = i;
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mbuf->buf = (char *)mbuf + sizeof(struct mbuf_t);
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mbuf->len = payload;
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mbuf->next = NULL;
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pool->free = size;
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PCIE_INFO("%s(0x%p, %d)\n", __func__, pool, pool->free);
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return 0;
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}
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int mbuf_pool_deinit(struct buffer_pool *pool)
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{
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memset(pool->mem, 0x00, (sizeof(struct mbuf_t) +
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pool->payload) * pool->size);
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kfree(pool->mem);
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return 0;
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}
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int mchn_hw_pop_link(int chn, void *head, void *tail, int num)
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{
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struct mchn_info_t *mchn = mchn_info();
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if (mchn->ops[chn] == NULL) {
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WARN_ON(1);
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return -1;
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}
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if (mchn->ops[chn]->hif_type == HW_TYPE_PCIE)
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edma_tp_count(chn, head, tail, num);
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return mchn->ops[chn]->pop_link(chn, (struct mbuf_t *)head,
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(struct mbuf_t *)tail, num);
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}
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EXPORT_SYMBOL(mchn_hw_pop_link);
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int mchn_hw_tx_complete(int chn, int timeout)
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{
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struct mchn_info_t *mchn = mchn_info();
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if (mchn->ops[chn] == NULL)
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WARN_ON(1);
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if (mchn->ops[chn]->tx_complete)
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mchn->ops[chn]->tx_complete(chn, timeout);
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return 0;
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}
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EXPORT_SYMBOL(mchn_hw_tx_complete);
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int mchn_hw_req_push_link(int chn, int need)
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{
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int ret;
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struct mbuf_t *head = NULL, *tail = NULL;
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struct mchn_info_t *mchn = mchn_info();
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if (mchn->ops[chn] == NULL)
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return -1;
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ret = mchn->ops[chn]->push_link(chn, &head, &tail, &need);
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if (ret != 0)
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return ret;
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ret = mchn_push_link(chn, (void *)head, (void *)tail, need);
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return ret;
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}
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EXPORT_SYMBOL(mchn_hw_req_push_link);
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int mchn_hw_cb_in_irq(int chn)
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{
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if (!g_mchn.ops[chn]) {
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PCIE_ERR("%s: chn=%d is not register\n", __func__, chn);
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return -1;
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}
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return g_mchn.ops[chn]->cb_in_irq;
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}
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int mchn_hw_max_pending(int chn)
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{
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if (!g_mchn.ops[chn]) {
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PCIE_ERR("%s: chn=%d is not register\n", __func__, chn);
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return -1;
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}
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return g_mchn.ops[chn]->max_pending;
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}
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int mchn_push_link(int chn, struct mbuf_t *head, struct mbuf_t *tail, int num)
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{
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int ret = -1;
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struct mchn_info_t *mchn = mchn_info();
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if ((chn >= 16) || (mchn->ops[chn] == NULL) || (head == NULL) ||
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(tail == NULL) || (num > mchn->ops[chn]->pool_size)) {
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WARN_ON(1);
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return -1;
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}
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switch (mchn->ops[chn]->hif_type) {
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case HW_TYPE_SDIO:
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break;
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case HW_TYPE_PCIE:
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if (mchn_hw_max_pending(chn) > 0)
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ret = edma_push_link_async(chn, (void *)head,
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(void *)tail, num);
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else
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ret = edma_push_link(chn, (void *)head,
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(void *)tail, num);
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break;
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default:
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break;
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}
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return ret;
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}
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EXPORT_SYMBOL(mchn_push_link);
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int mchn_push_link_wait_complete(int chn, struct mbuf_t *head,
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struct mbuf_t *tail, int num, int timeout)
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{
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int ret = -1;
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struct mchn_info_t *mchn = mchn_info();
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if ((chn >= 32) || (mchn->ops[chn] == NULL)) {
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WARN_ON(1);
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return -1;
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}
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switch (mchn->ops[chn]->hif_type) {
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case HW_TYPE_SDIO:
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break;
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case HW_TYPE_PCIE:
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ret = edma_push_link_wait_complete(chn, (void *)head,
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(void *)tail, num, timeout);
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break;
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default:
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break;
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}
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return ret;
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}
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EXPORT_SYMBOL(mchn_push_link_wait_complete);
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int mchn_init(struct mchn_ops_t *ops)
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{
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int ret = -1;
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struct mchn_info_t *mchn = mchn_info();
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PCIE_INFO("[+]%s(%d, %d)\n", __func__, ops->channel, ops->hif_type);
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if ((mchn->ops[ops->channel] != NULL) ||
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((ops->hif_type != HW_TYPE_SDIO) &&
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(ops->hif_type != HW_TYPE_PCIE))) {
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PCIE_INFO("%s err, hif_type %d\n", __func__, ops->hif_type);
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WARN_ON(1);
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return -1;
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}
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mchn->ops[ops->channel] = ops;
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switch (ops->hif_type) {
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case HW_TYPE_SDIO:
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ret = 0;
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break;
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case HW_TYPE_PCIE:
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ret = edma_chn_init(ops->channel, 0, ops->inout,
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ops->pool_size);
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break;
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default:
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break;
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}
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if ((ret == 0) && (ops->pool_size > 0))
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ret = mbuf_pool_init(&(mchn->chn_public[ops->channel].pool),
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ops->pool_size, 0);
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PCIE_INFO("[-]%s(%d)\n", __func__, ops->channel);
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return ret;
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}
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EXPORT_SYMBOL(mchn_init);
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int mchn_deinit(struct mchn_ops_t *ops)
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{
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int ret = 0;
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struct mchn_info_t *mchn = mchn_info();
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PCIE_INFO("[+]%s(%d, %d)\n", __func__, ops->channel, ops->hif_type);
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if ((mchn->ops[ops->channel] == NULL) ||
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((ops->hif_type != HW_TYPE_SDIO) &&
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(ops->hif_type != HW_TYPE_PCIE))) {
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PCIE_ERR("%s err\n", __func__);
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return -1;
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}
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switch (ops->hif_type) {
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case HW_TYPE_SDIO:
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break;
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case HW_TYPE_PCIE:
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break;
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default:
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break;
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}
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if (ops->pool_size > 0)
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ret = mbuf_pool_deinit(&(mchn->chn_public[ops->channel].pool));
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mchn->ops[ops->channel] = NULL;
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PCIE_INFO("[-]%s(%d)\n", __func__, ops->channel);
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return ret;
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}
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EXPORT_SYMBOL(mchn_deinit);
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