/*
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* Copyright (C) 2017 Spreadtrum Communications Inc.
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*
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* Filename : wcn_integrate_platform.h
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* Abstract : This file is a implementation for driver of integrated marlin:
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* The marlin chip and GNSS chip were integrated with AP chipset.
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*
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* Authors : yaoguang.chen
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*
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __WCN_INTEGRATE_H__
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#define __WCN_INTEGRATE_H__
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/file.h>
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#include <linux/firmware.h>
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#include <linux/fs.h>
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#include <linux/kernel.h>
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#include <linux/kthread.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_gpio.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/proc_fs.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/unistd.h>
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#include <linux/vmalloc.h>
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#include <linux/workqueue.h>
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#include "linux/sipc.h"
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#include "linux/sprd_otp.h"
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#include "wcn_integrate_dev.h"
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#define REGMAP_UPDATE_BITS_ENABLE 0 /* It can't work well. */
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#define MDBG_CACHE_FLAG_VALUE (0xcdcddcdc)
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#define WCN_AON_CHIP_ID0 0x00E0
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#define WCN_AON_CHIP_ID1 0x00E4
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#define WCN_AON_PLATFORM_ID0 0x00E8
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#define WCN_AON_PLATFORM_ID1 0x00EC
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#define WCN_AON_CHIP_ID 0x00FC
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#define WCN_AON_VERSION_ID 0x00F8
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#define PIKE2_CHIP_ID0 0x32000000 /* 2 */
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#define PIKE2_CHIP_ID1 0x50696B65 /* Pike */
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#define SHARKLE_CHIP_ID0 0x6B4C4500 /* kle */
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#define SHARKLE_CHIP_ID1 0x53686172 /* Shar */
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#define SHARKL3_CHIP_ID0 0x6B4C3300 /* kl3 */
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#define SHARKL3_CHIP_ID1 0x53686172 /* Shar */
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#define AON_CHIP_ID_AA 0x96360000
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#define AON_CHIP_ID_AC 0x96360002
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struct platform_chip_id {
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u32 aon_chip_id0;
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u32 aon_chip_id1;
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u32 aon_platform_id0;
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u32 aon_platform_id1;
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u32 aon_chip_id;
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};
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enum {
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WCN_PLATFORM_TYPE_SHARKLE,
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WCN_PLATFORM_TYPE_PIKE2,
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WCN_PLATFORM_TYPE_SHARKL3,
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WCN_PLATFORM_TYPE,
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};
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enum wcn_gnss_type {
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WCN_GNSS_TYPE_INVALID,
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WCN_GNSS_TYPE_GL,
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WCN_GNSS_TYPE_BD,
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};
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enum wcn_aon_chip_id {
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WCN_AON_CHIP_ID_INVALID,
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WCN_SHARKLE_CHIP_AA_OR_AB,
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WCN_SHARKLE_CHIP_AC,
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WCN_SHARKLE_CHIP_AD,
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WCN_PIKE2_CHIP,
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WCN_PIKE2_CHIP_AA,
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WCN_PIKE2_CHIP_AB,
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};
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struct wcn_chip_type {
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u32 chipid;
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enum wcn_aon_chip_id chiptype;
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};
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#define WCN_SPECIAL_SHARME_MEM_ADDR (0x0017c000)
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struct wifi_special_share_mem {
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struct wifi_calibration calibration_data;
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u32 efuse[WIFI_EFUSE_BLOCK_COUNT];
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u32 calibration_flag;
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};
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struct marlin_special_share_mem {
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u32 init_status;
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u32 loopcheck_cnt;
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};
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struct gnss_special_share_mem {
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u32 calibration_flag;
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u32 efuse[GNSS_EFUSE_BLOCK_COUNT];
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};
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struct wcn_special_share_mem {
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/* 0x17c000 */
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struct wifi_special_share_mem wifi;
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/* 0x17cf54 */
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struct marlin_special_share_mem marlin;
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/* 0x17cf5c */
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u32 include_gnss;
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/* 0x17cf60 */
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u32 gnss_flag_addr;
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/* 0x17cf64 */
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u32 cp2_sleep_status;
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/* 0x17cf68 */
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u32 sleep_flag_addr;
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/* 0x17cf6c */
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u32 efuse_temper_magic;
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/* 0x17cf70 */
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u32 efuse_temper_val;
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/* 0x17cf74 */
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struct gnss_special_share_mem gnss;
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};
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typedef int (*marlin_reset_callback) (void *para);
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extern struct platform_chip_id g_platform_chip_id;
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extern char functionmask[8];
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extern struct wcn_special_share_mem *s_wssm_phy_offset_p;
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int wcn_write_data_to_phy_addr(phys_addr_t phy_addr,
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void *src_data, u32 size);
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int wcn_read_data_from_phy_addr(phys_addr_t phy_addr,
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void *tar_data, u32 size);
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void *wcn_mem_ram_vmap_nocache(phys_addr_t start, size_t size,
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unsigned int *count);
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void wcn_mem_ram_unmap(const void *mem, unsigned int count);
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u32 wcn_platform_chip_id(void);
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u32 wcn_platform_chip_type(void);
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u32 wcn_get_cp2_comm_rx_count(void);
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phys_addr_t wcn_get_btwf_base_addr(void);
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phys_addr_t wcn_get_btwf_sleep_addr(void);
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phys_addr_t wcn_get_btwf_init_status_addr(void);
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int wcn_get_btwf_power_status(void);
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void wcn_regmap_read(struct regmap *cur_regmap,
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u32 reg,
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unsigned int *val);
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void wcn_regmap_raw_write_bit(struct regmap *cur_regmap,
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u32 reg,
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unsigned int val);
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struct regmap *wcn_get_btwf_regmap(u32 regmap_type);
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struct regmap *wcn_get_gnss_regmap(u32 regmap_type);
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phys_addr_t wcn_get_gnss_base_addr(void);
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bool wcn_get_download_status(void);
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void wcn_set_download_status(bool status);
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u32 gnss_get_boot_status(void);
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void gnss_set_boot_status(u32 status);
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int marlin_get_module_status(void);
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int wcn_get_module_status_changed(void);
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void wcn_set_module_status_changed(bool status);
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int marlin_reset_register_notify(void *callback_func, void *para);
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int marlin_reset_unregister_notify(void);
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void wcn_set_module_state(bool status);
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int wcn_send_force_sleep_cmd(struct wcn_device *wcn_dev);
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u32 wcn_get_sleep_status(struct wcn_device *wcn_dev, int force_sleep);
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void wcn_power_domain_set(struct wcn_device *wcn_dev, u32 set_type);
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void wcn_xtl_auto_sel(bool enable);
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int wcn_power_enable_sys_domain(bool enable);
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void wcn_sys_soft_reset(void);
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void wcn_sys_ctrl_26m(bool enable);
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void wcn_clock_ctrl(bool enable);
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void wcn_sys_soft_release(void);
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void wcn_sys_deep_sleep_en(void);
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void wcn_power_set_vddcon(u32 value);
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int wcn_power_enable_vddcon(bool enable);
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void wcn_power_set_vddwifipa(u32 value);
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int wcn_marlin_power_enable_vddwifipa(bool enable);
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u32 wcn_parse_platform_chip_id(struct wcn_device *wcn_dev);
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void mdbg_hold_cpu(void);
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enum wcn_aon_chip_id wcn_get_aon_chip_id(void);
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#endif
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