/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Arm Limited. All rights reserved.
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*
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* Author: Suzuki K Poulose <suzuki.poulose@arm.com>
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*/
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#ifndef _CORESIGHT_CATU_H
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#define _CORESIGHT_CATU_H
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#include "coresight-priv.h"
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/* Register offset from base */
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#define CATU_CONTROL 0x000
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#define CATU_MODE 0x004
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#define CATU_AXICTRL 0x008
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#define CATU_IRQEN 0x00c
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#define CATU_SLADDRLO 0x020
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#define CATU_SLADDRHI 0x024
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#define CATU_INADDRLO 0x028
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#define CATU_INADDRHI 0x02c
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#define CATU_STATUS 0x100
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#define CATU_DEVARCH 0xfbc
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#define CATU_CONTROL_ENABLE 0
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#define CATU_MODE_PASS_THROUGH 0U
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#define CATU_MODE_TRANSLATE 1U
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#define CATU_AXICTRL_ARCACHE_SHIFT 4
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#define CATU_AXICTRL_ARCACHE_MASK 0xf
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#define CATU_AXICTRL_ARPROT_MASK 0x3
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#define CATU_AXICTRL_ARCACHE(arcache) \
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(((arcache) & CATU_AXICTRL_ARCACHE_MASK) << CATU_AXICTRL_ARCACHE_SHIFT)
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#define CATU_AXICTRL_VAL(arcache, arprot) \
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(CATU_AXICTRL_ARCACHE(arcache) | ((arprot) & CATU_AXICTRL_ARPROT_MASK))
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#define AXI3_AxCACHE_WB_READ_ALLOC 0x7
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/*
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* AXI - ARPROT bits:
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* See AMBA AXI & ACE Protocol specification (ARM IHI 0022E)
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* sectionA4.7 Access Permissions.
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*
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* Bit 0: 0 - Unprivileged access, 1 - Privileged access
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* Bit 1: 0 - Secure access, 1 - Non-secure access.
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* Bit 2: 0 - Data access, 1 - instruction access.
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*
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* CATU AXICTRL:ARPROT[2] is res0 as we always access data.
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*/
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#define CATU_OS_ARPROT 0x2
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#define CATU_OS_AXICTRL \
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CATU_AXICTRL_VAL(AXI3_AxCACHE_WB_READ_ALLOC, CATU_OS_ARPROT)
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#define CATU_STATUS_READY 8
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#define CATU_STATUS_ADRERR 0
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#define CATU_STATUS_AXIERR 4
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#define CATU_IRQEN_ON 0x1
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#define CATU_IRQEN_OFF 0x0
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struct catu_drvdata {
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void __iomem *base;
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struct coresight_device *csdev;
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int irq;
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};
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#define CATU_REG32(name, offset) \
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static inline u32 \
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catu_read_##name(struct catu_drvdata *drvdata) \
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{ \
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return coresight_read_reg_pair(drvdata->base, offset, -1); \
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} \
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static inline void \
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catu_write_##name(struct catu_drvdata *drvdata, u32 val) \
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{ \
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coresight_write_reg_pair(drvdata->base, val, offset, -1); \
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}
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#define CATU_REG_PAIR(name, lo_off, hi_off) \
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static inline u64 \
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catu_read_##name(struct catu_drvdata *drvdata) \
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{ \
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return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \
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} \
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static inline void \
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catu_write_##name(struct catu_drvdata *drvdata, u64 val) \
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{ \
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coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \
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}
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CATU_REG32(control, CATU_CONTROL);
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CATU_REG32(mode, CATU_MODE);
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CATU_REG32(irqen, CATU_IRQEN);
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CATU_REG32(axictrl, CATU_AXICTRL);
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CATU_REG_PAIR(sladdr, CATU_SLADDRLO, CATU_SLADDRHI)
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CATU_REG_PAIR(inaddr, CATU_INADDRLO, CATU_INADDRHI)
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static inline bool coresight_is_catu_device(struct coresight_device *csdev)
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{
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if (!IS_ENABLED(CONFIG_CORESIGHT_CATU))
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return false;
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if (csdev->type != CORESIGHT_DEV_TYPE_HELPER)
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return false;
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if (csdev->subtype.helper_subtype != CORESIGHT_DEV_SUBTYPE_HELPER_CATU)
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return false;
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return true;
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}
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#endif
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