/*
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* Copyright 2019 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <subdev/mmu.h>
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#include <nvfw/flcn.h>
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void
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gp108_acr_hsfw_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
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{
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struct flcn_bl_dmem_desc_v2 hsdesc = {
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.ctx_dma = FALCON_DMAIDX_VIRT,
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.code_dma_base = hsf->vma->addr,
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.non_sec_code_off = hsf->non_sec_addr,
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.non_sec_code_size = hsf->non_sec_size,
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.sec_code_off = hsf->sec_addr,
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.sec_code_size = hsf->sec_size,
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.code_entry_point = 0,
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.data_dma_base = hsf->vma->addr + hsf->data_addr,
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.data_size = hsf->data_size,
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.argc = 0,
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.argv = 0,
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};
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flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hsdesc);
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nvkm_falcon_load_dmem(hsf->falcon, &hsdesc, 0, sizeof(hsdesc), 0);
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}
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const struct nvkm_acr_hsf_func
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gp108_acr_unload_0 = {
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.load = gm200_acr_unload_load,
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.boot = gm200_acr_unload_boot,
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.bld = gp108_acr_hsfw_bld,
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};
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MODULE_FIRMWARE("nvidia/gp108/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/gp108/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gv100/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/gv100/acr/ucode_unload.bin");
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static const struct nvkm_acr_hsf_fwif
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gp108_acr_unload_fwif[] = {
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{ 0, nvkm_acr_hsfw_load, &gp108_acr_unload_0 },
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{}
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};
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static const struct nvkm_acr_hsf_func
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gp108_acr_load_0 = {
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.load = gp102_acr_load_load,
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.boot = gm200_acr_load_boot,
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.bld = gp108_acr_hsfw_bld,
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};
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MODULE_FIRMWARE("nvidia/gp108/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp108/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gv100/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gv100/acr/ucode_load.bin");
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static const struct nvkm_acr_hsf_fwif
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gp108_acr_load_fwif[] = {
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{ 0, nvkm_acr_hsfw_load, &gp108_acr_load_0 },
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{}
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};
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static const struct nvkm_acr_func
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gp108_acr = {
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.load = gp108_acr_load_fwif,
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.unload = gp108_acr_unload_fwif,
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.wpr_parse = gp102_acr_wpr_parse,
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.wpr_layout = gp102_acr_wpr_layout,
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.wpr_alloc = gp102_acr_wpr_alloc,
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.wpr_build = gp102_acr_wpr_build,
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.wpr_patch = gp102_acr_wpr_patch,
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.wpr_check = gm200_acr_wpr_check,
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.init = gm200_acr_init,
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};
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static const struct nvkm_acr_fwif
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gp108_acr_fwif[] = {
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{ 0, gp102_acr_load, &gp108_acr },
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{ -1, gm200_acr_nofw, &gm200_acr },
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{}
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};
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int
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gp108_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr)
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{
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return nvkm_acr_new_(gp108_acr_fwif, device, index, pacr);
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}
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