/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file contains defines for the
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* Micro Memory MM5415
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* family PCI Memory Module with Battery Backup.
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*
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* Copyright Micro Memory INC 2001. All rights reserved.
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*/
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#ifndef _DRIVERS_BLOCK_MM_H
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#define _DRIVERS_BLOCK_MM_H
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#define IRQ_TIMEOUT (1 * HZ)
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/* CSR register definition */
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#define MEMCTRLSTATUS_MAGIC 0x00
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#define MM_MAGIC_VALUE (unsigned char)0x59
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#define MEMCTRLSTATUS_BATTERY 0x04
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#define BATTERY_1_DISABLED 0x01
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#define BATTERY_1_FAILURE 0x02
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#define BATTERY_2_DISABLED 0x04
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#define BATTERY_2_FAILURE 0x08
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#define MEMCTRLSTATUS_MEMORY 0x07
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#define MEM_128_MB 0xfe
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#define MEM_256_MB 0xfc
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#define MEM_512_MB 0xf8
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#define MEM_1_GB 0xf0
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#define MEM_2_GB 0xe0
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#define MEMCTRLCMD_LEDCTRL 0x08
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#define LED_REMOVE 2
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#define LED_FAULT 4
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#define LED_POWER 6
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#define LED_FLIP 255
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#define LED_OFF 0x00
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#define LED_ON 0x01
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#define LED_FLASH_3_5 0x02
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#define LED_FLASH_7_0 0x03
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#define LED_POWER_ON 0x00
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#define LED_POWER_OFF 0x01
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#define USER_BIT1 0x01
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#define USER_BIT2 0x02
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#define MEMORY_INITIALIZED USER_BIT1
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#define MEMCTRLCMD_ERRCTRL 0x0C
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#define EDC_NONE_DEFAULT 0x00
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#define EDC_NONE 0x01
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#define EDC_STORE_READ 0x02
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#define EDC_STORE_CORRECT 0x03
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#define MEMCTRLCMD_ERRCNT 0x0D
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#define MEMCTRLCMD_ERRSTATUS 0x0E
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#define ERROR_DATA_LOG 0x20
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#define ERROR_ADDR_LOG 0x28
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#define ERROR_COUNT 0x3D
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#define ERROR_SYNDROME 0x3E
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#define ERROR_CHECK 0x3F
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#define DMA_PCI_ADDR 0x40
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#define DMA_LOCAL_ADDR 0x48
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#define DMA_TRANSFER_SIZE 0x50
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#define DMA_DESCRIPTOR_ADDR 0x58
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#define DMA_SEMAPHORE_ADDR 0x60
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#define DMA_STATUS_CTRL 0x68
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#define DMASCR_GO 0x00001
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#define DMASCR_TRANSFER_READ 0x00002
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#define DMASCR_CHAIN_EN 0x00004
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#define DMASCR_SEM_EN 0x00010
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#define DMASCR_DMA_COMP_EN 0x00020
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#define DMASCR_CHAIN_COMP_EN 0x00040
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#define DMASCR_ERR_INT_EN 0x00080
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#define DMASCR_PARITY_INT_EN 0x00100
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#define DMASCR_ANY_ERR 0x00800
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#define DMASCR_MBE_ERR 0x01000
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#define DMASCR_PARITY_ERR_REP 0x02000
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#define DMASCR_PARITY_ERR_DET 0x04000
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#define DMASCR_SYSTEM_ERR_SIG 0x08000
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#define DMASCR_TARGET_ABT 0x10000
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#define DMASCR_MASTER_ABT 0x20000
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#define DMASCR_DMA_COMPLETE 0x40000
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#define DMASCR_CHAIN_COMPLETE 0x80000
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/*
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3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE
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READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA
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TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE
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TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS
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(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
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AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING
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DMA READ OPERATIONS.
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*/
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#define DMASCR_READ 0x60000000
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#define DMASCR_READLINE 0xE0000000
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#define DMASCR_READMULTI 0xC0000000
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#define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR)
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#define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR)
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#define WINDOWMAP_WINNUM 0x7B
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#define DMA_READ_FROM_HOST 0
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#define DMA_WRITE_TO_HOST 1
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struct mm_dma_desc {
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__le64 pci_addr;
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__le64 local_addr;
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__le32 transfer_size;
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u32 zero1;
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__le64 next_desc_addr;
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__le64 sem_addr;
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__le32 control_bits;
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u32 zero2;
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dma_addr_t data_dma_handle;
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/* Copy of the bits */
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__le64 sem_control_bits;
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} __attribute__((aligned(8)));
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/* bits for card->flags */
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#define UM_FLAG_DMA_IN_REGS 1
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#define UM_FLAG_NO_BYTE_STATUS 2
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#define UM_FLAG_NO_BATTREG 4
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#define UM_FLAG_NO_BATT 8
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#endif
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