/*
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* Copyright 2013, 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Driver for the Vitesse VSC9953 L2 Switch
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*/
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#ifndef _VSC9953_H_
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#define _VSC9953_H_
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#include <config.h>
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#include <miiphy.h>
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#include <asm/types.h>
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#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
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#define VSC9953_SYS_OFFSET 0x010000
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#define VSC9953_REW_OFFSET 0x030000
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#define VSC9953_DEV_GMII_OFFSET 0x100000
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#define VSC9953_QSYS_OFFSET 0x200000
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#define VSC9953_ANA_OFFSET 0x280000
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#define VSC9953_DEVCPU_GCB 0x070000
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#define VSC9953_ES0 0x040000
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#define VSC9953_IS1 0x050000
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#define VSC9953_IS2 0x060000
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#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
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#define VSC9953_PHY_REGS_OFFST 0x0000AC
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/* Macros for vsc9953_chip_regs.soft_rst register */
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#define VSC9953_SOFT_SWC_RST_ENA 0x00000001
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/* Macros for vsc9953_sys_sys.reset_cfg register */
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#define VSC9953_CORE_ENABLE 0x80
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#define VSC9953_MEM_ENABLE 0x40
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#define VSC9953_MEM_INIT 0x20
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/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
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#define VSC9953_MAC_ENA_CFG 0x00000011
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/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
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#define VSC9953_MAC_MODE_CFG 0x00000011
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/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
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#define VSC9953_MAC_IFG_CFG 0x00000515
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/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
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#define VSC9953_MAC_HDX_CFG 0x00001043
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/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
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#define VSC9953_MAC_MAX_LEN 0x000005ee
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/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
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#define VSC9953_CLOCK_CFG 0x00000001
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#define VSC9953_CLOCK_CFG_1000M 0x00000001
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/* Macros for vsc9953_sys_sys.front_port_mode register */
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#define VSC9953_FRONT_PORT_MODE 0x00000000
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/* Macros for vsc9953_ana_pfc.pfc_cfg register */
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#define VSC9953_PFC_FC 0x00000001
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#define VSC9953_PFC_FC_QSGMII 0x00000000
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/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
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#define VSC9953_MAC_FC_CFG 0x04700000
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#define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
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/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
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#define VSC9953_PAUSE_CFG 0x001ffffe
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/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
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#define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
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/* Macros for vsc9953_sys_sys.stat_cfg register */
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#define VSC9953_STAT_CLEAR_RX 0x00000400
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#define VSC9953_STAT_CLEAR_TX 0x00000800
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#define VSC9953_STAT_CLEAR_DR 0x00001000
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/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
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#define VSC9953_VCAP_MV_CFG 0x0000ffff
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#define VSC9953_VCAP_UPDATE_CTRL 0x01000004
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/* Macros for register vsc9953_ana_ana_tables.mac_access register */
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#define VSC9953_MAC_CMD_IDLE 0x00000000
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#define VSC9953_MAC_CMD_LEARN 0x00000001
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#define VSC9953_MAC_CMD_FORGET 0x00000002
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#define VSC9953_MAC_CMD_AGE 0x00000003
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#define VSC9953_MAC_CMD_NEXT 0x00000004
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#define VSC9953_MAC_CMD_READ 0x00000006
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#define VSC9953_MAC_CMD_WRITE 0x00000007
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#define VSC9953_MAC_CMD_MASK 0x00000007
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#define VSC9953_MAC_CMD_VALID 0x00000800
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#define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000
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#define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200
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#define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
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#define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
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#define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600
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#define VSC9953_MAC_DESTIDX_MASK 0x000001f8
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#define VSC9953_MAC_VID_MASK 0x1fff0000
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#define VSC9953_MAC_MACH_MASK 0x0000ffff
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/* Macros for vsc9953_ana_port.vlan_cfg register */
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#define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
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#define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
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#define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000
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#define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000
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#define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
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/* Macros for vsc9953_rew_port.port_vlan_cfg register */
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#define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
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/* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
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#define VSC9953_ANA_TBL_VID_MASK 0x00000fff
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/* Macros for vsc9953_ana_ana_tables.vlan_access register */
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#define VSC9953_VLAN_PORT_MASK 0x00001ffc
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#define VSC9953_VLAN_CMD_MASK 0x00000003
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#define VSC9953_VLAN_CMD_IDLE 0x00000000
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#define VSC9953_VLAN_CMD_READ 0x00000001
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#define VSC9953_VLAN_CMD_WRITE 0x00000002
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#define VSC9953_VLAN_CMD_INIT 0x00000003
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/* Macros for vsc9953_ana_port.port_cfg register */
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#define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
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#define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
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#define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
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#define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
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#define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c
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/* Macros for vsc9953_qsys_sys.switch_port_mode register */
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#define VSC9953_PORT_ENA 0x00002000
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/* Macros for vsc9953_ana_ana.agen_ctrl register */
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#define VSC9953_FID_MASK_ALL 0x00fff000
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/* Macros for vsc9953_ana_ana.adv_learn register */
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#define VSC9953_VLAN_CHK 0x00000400
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/* Macros for vsc9953_ana_ana.auto_age register */
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#define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe
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/* Macros for vsc9953_rew_port.port_tag_cfg register */
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#define VSC9953_TAG_CFG_MASK 0x00000180
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#define VSC9953_TAG_CFG_NONE 0x00000000
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#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
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#define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
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#define VSC9953_TAG_CFG_ALL 0x00000180
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#define VSC9953_TAG_VID_PVID 0x00000010
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/* Macros for vsc9953_ana_ana.anag_efil register */
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#define VSC9953_AGE_PORT_EN 0x00080000
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#define VSC9953_AGE_PORT_MASK 0x0007c000
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#define VSC9953_AGE_VID_EN 0x00002000
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#define VSC9953_AGE_VID_MASK 0x00001fff
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/* Macros for vsc9953_ana_ana_tables.mach_data register */
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#define VSC9953_MACHDATA_VID_MASK 0x1fff0000
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/* Macros for vsc9953_ana_common.aggr_cfg register */
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#define VSC9953_AC_RND_ENA 0x00000080
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#define VSC9953_AC_DMAC_ENA 0x00000040
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#define VSC9953_AC_SMAC_ENA 0x00000020
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#define VSC9953_AC_IP6_LBL_ENA 0x00000010
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#define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008
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#define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004
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#define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002
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#define VSC9953_AC_MASK 0x000000fe
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/* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
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#define VSC9953_PGID_PORT_MASK 0x000003ff
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#define VSC9953_MAX_PORTS 10
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#define VSC9953_PORT_CHECK(port) \
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(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
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#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
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( \
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(port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
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) ? 0 : 1 \
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)
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#define VSC9953_MAX_VLAN 4096
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#define VSC9953_VLAN_CHECK(vid) \
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(((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
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#define VSC9953_DEFAULT_AGE_TIME 300
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#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
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#define MIIMIND_OPR_PEND 0x00000004
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struct vsc9953_mdio_info {
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struct vsc9953_mii_mng *regs;
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char *name;
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};
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/* VSC9953 ANA structure */
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struct vsc9953_ana_port {
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u32 vlan_cfg;
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u32 drop_cfg;
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u32 qos_cfg;
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u32 vcap_cfg;
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u32 vcap_s1_key_cfg[3];
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u32 vcap_s2_cfg;
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u32 qos_pcp_dei_map_cfg[16];
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u32 cpu_fwd_cfg;
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u32 cpu_fwd_bpdu_cfg;
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u32 cpu_fwd_garp_cfg;
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u32 cpu_fwd_ccm_cfg;
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u32 port_cfg;
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u32 pol_cfg;
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u32 reserved[34];
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};
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struct vsc9953_ana_pol {
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u32 pol_pir_cfg;
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u32 pol_cir_cfg;
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u32 pol_mode_cfg;
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u32 pol_pir_state;
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u32 pol_cir_state;
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u32 reserved1[3];
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};
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struct vsc9953_ana_ana_tables {
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u32 entry_lim[11];
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u32 an_moved;
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u32 mach_data;
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u32 macl_data;
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u32 mac_access;
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u32 mact_indx;
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u32 vlan_access;
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u32 vlan_tidx;
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};
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struct vsc9953_ana_ana {
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u32 adv_learn;
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u32 vlan_mask;
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u32 reserved;
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u32 anag_efil;
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u32 an_events;
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u32 storm_limit_burst;
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u32 storm_limit_cfg[4];
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u32 isolated_prts;
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u32 community_ports;
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u32 auto_age;
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u32 mac_options;
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u32 learn_disc;
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u32 agen_ctrl;
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u32 mirror_ports;
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u32 emirror_ports;
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u32 flooding;
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u32 flooding_ipmc;
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u32 sflow_cfg[11];
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u32 port_mode[12];
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};
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#define PGID_DST_START 0
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#define PGID_AGGR_START 64
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#define PGID_SRC_START 80
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struct vsc9953_ana_pgid {
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u32 port_grp_id[91];
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};
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struct vsc9953_ana_pfc {
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u32 pfc_cfg;
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u32 reserved1[15];
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};
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struct vsc9953_ana_pol_misc {
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u32 pol_flowc[10];
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u32 reserved1[17];
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u32 pol_hyst;
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};
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struct vsc9953_ana_common {
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u32 aggr_cfg;
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u32 cpuq_cfg;
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u32 cpuq_8021_cfg;
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u32 dscp_cfg;
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u32 dscp_rewr_cfg;
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u32 vcap_rng_type_cfg;
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u32 vcap_rng_val_cfg;
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u32 discard_cfg;
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u32 fid_cfg;
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};
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struct vsc9953_analyzer {
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struct vsc9953_ana_port port[11];
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u32 reserved1[9536];
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struct vsc9953_ana_pol pol[164];
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struct vsc9953_ana_ana_tables ana_tables;
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u32 reserved2[14];
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struct vsc9953_ana_ana ana;
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u32 reserved3[21];
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struct vsc9953_ana_pgid port_id_tbl;
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u32 reserved4[549];
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struct vsc9953_ana_pfc pfc[10];
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struct vsc9953_ana_pol_misc pol_misc;
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u32 reserved5[196];
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struct vsc9953_ana_common common;
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};
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/* END VSC9953 ANA structure t*/
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/* VSC9953 DEV_GMII structure */
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struct vsc9953_dev_gmii_port_mode {
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u32 clock_cfg;
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u32 port_misc;
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u32 reserved1;
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u32 eee_cfg;
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};
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struct vsc9953_dev_gmii_mac_cfg_status {
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u32 mac_ena_cfg;
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u32 mac_mode_cfg;
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u32 mac_maxlen_cfg;
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u32 mac_tags_cfg;
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u32 mac_adv_chk_cfg;
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u32 mac_ifg_cfg;
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u32 mac_hdx_cfg;
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u32 mac_fc_mac_low_cfg;
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u32 mac_fc_mac_high_cfg;
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u32 mac_sticky;
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};
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struct vsc9953_dev_gmii {
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struct vsc9953_dev_gmii_port_mode port_mode;
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struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
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};
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/* END VSC9953 DEV_GMII structure */
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/* VSC9953 QSYS structure */
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struct vsc9953_qsys_hsch {
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u32 cir_cfg;
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u32 reserved1;
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u32 se_cfg;
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u32 se_dwrr_cfg[8];
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u32 cir_state;
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u32 reserved2[20];
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};
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struct vsc9953_qsys_sys {
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u32 port_mode[12];
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u32 switch_port_mode[11];
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u32 stat_cnt_cfg;
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u32 eee_cfg[10];
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u32 eee_thrs;
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u32 igr_no_sharing;
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u32 egr_no_sharing;
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u32 sw_status[11];
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u32 ext_cpu_cfg;
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u32 cpu_group_map;
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u32 reserved1[23];
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};
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struct vsc9953_qsys_qos_cfg {
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u32 red_profile[16];
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u32 res_qos_mode;
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};
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struct vsc9953_qsys_drop_cfg {
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u32 egr_drop_mode;
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};
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struct vsc9953_qsys_mmgt {
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u32 eq_cntrl;
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u32 reserved1;
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};
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struct vsc9953_qsys_hsch_misc {
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u32 hsch_misc_cfg;
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u32 reserved1[546];
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};
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struct vsc9953_qsys_res_ctrl {
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u32 res_cfg;
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u32 res_stat;
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};
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struct vsc9953_qsys_reg {
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struct vsc9953_qsys_hsch hsch[108];
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struct vsc9953_qsys_sys sys;
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struct vsc9953_qsys_qos_cfg qos_cfg;
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struct vsc9953_qsys_drop_cfg drop_cfg;
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struct vsc9953_qsys_mmgt mmgt;
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struct vsc9953_qsys_hsch_misc hsch_misc;
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struct vsc9953_qsys_res_ctrl res_ctrl[1024];
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};
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/* END VSC9953 QSYS structure */
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/* VSC9953 SYS structure */
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struct vsc9953_rx_cntrs {
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u32 c_rx_oct;
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u32 c_rx_uc;
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u32 c_rx_mc;
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u32 c_rx_bc;
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u32 c_rx_short;
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u32 c_rx_frag;
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u32 c_rx_jabber;
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u32 c_rx_crc;
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u32 c_rx_symbol_err;
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u32 c_rx_sz_64;
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u32 c_rx_sz_65_127;
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u32 c_rx_sz_128_255;
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u32 c_rx_sz_256_511;
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u32 c_rx_sz_512_1023;
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u32 c_rx_sz_1024_1526;
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u32 c_rx_sz_jumbo;
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u32 c_rx_pause;
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u32 c_rx_control;
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u32 c_rx_long;
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u32 c_rx_cat_drop;
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u32 c_rx_red_prio_0;
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u32 c_rx_red_prio_1;
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u32 c_rx_red_prio_2;
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u32 c_rx_red_prio_3;
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u32 c_rx_red_prio_4;
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u32 c_rx_red_prio_5;
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u32 c_rx_red_prio_6;
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u32 c_rx_red_prio_7;
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u32 c_rx_yellow_prio_0;
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u32 c_rx_yellow_prio_1;
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u32 c_rx_yellow_prio_2;
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u32 c_rx_yellow_prio_3;
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u32 c_rx_yellow_prio_4;
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u32 c_rx_yellow_prio_5;
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u32 c_rx_yellow_prio_6;
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u32 c_rx_yellow_prio_7;
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u32 c_rx_green_prio_0;
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u32 c_rx_green_prio_1;
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u32 c_rx_green_prio_2;
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u32 c_rx_green_prio_3;
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u32 c_rx_green_prio_4;
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u32 c_rx_green_prio_5;
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u32 c_rx_green_prio_6;
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u32 c_rx_green_prio_7;
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u32 reserved[20];
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};
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struct vsc9953_tx_cntrs {
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u32 c_tx_oct;
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u32 c_tx_uc;
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u32 c_tx_mc;
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u32 c_tx_bc;
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u32 c_tx_col;
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u32 c_tx_drop;
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u32 c_tx_pause;
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u32 c_tx_sz_64;
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u32 c_tx_sz_65_127;
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u32 c_tx_sz_128_255;
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u32 c_tx_sz_256_511;
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u32 c_tx_sz_512_1023;
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u32 c_tx_sz_1024_1526;
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u32 c_tx_sz_jumbo;
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u32 c_tx_yellow_prio_0;
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u32 c_tx_yellow_prio_1;
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u32 c_tx_yellow_prio_2;
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u32 c_tx_yellow_prio_3;
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u32 c_tx_yellow_prio_4;
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u32 c_tx_yellow_prio_5;
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u32 c_tx_yellow_prio_6;
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u32 c_tx_yellow_prio_7;
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u32 c_tx_green_prio_0;
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u32 c_tx_green_prio_1;
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u32 c_tx_green_prio_2;
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u32 c_tx_green_prio_3;
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u32 c_tx_green_prio_4;
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u32 c_tx_green_prio_5;
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u32 c_tx_green_prio_6;
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u32 c_tx_green_prio_7;
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u32 c_tx_aged;
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u32 reserved[33];
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};
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struct vsc9953_drop_cntrs {
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u32 c_dr_local;
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u32 c_dr_tail;
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u32 c_dr_yellow_prio_0;
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u32 c_dr_yellow_prio_1;
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u32 c_dr_yellow_prio_2;
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u32 c_dr_yellow_prio_3;
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u32 c_dr_yellow_prio_4;
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u32 c_dr_yellow_prio_5;
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u32 c_dr_yellow_prio_6;
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u32 c_dr_yellow_prio_7;
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u32 c_dr_green_prio_0;
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u32 c_dr_green_prio_1;
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u32 c_dr_green_prio_2;
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u32 c_dr_green_prio_3;
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u32 c_dr_green_prio_4;
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u32 c_dr_green_prio_5;
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u32 c_dr_green_prio_6;
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u32 c_dr_green_prio_7;
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u32 reserved[46];
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};
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struct vsc9953_sys_stat {
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struct vsc9953_rx_cntrs rx_cntrs;
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struct vsc9953_tx_cntrs tx_cntrs;
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struct vsc9953_drop_cntrs drop_cntrs;
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u32 reserved1[6];
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};
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struct vsc9953_sys_sys {
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u32 reset_cfg;
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u32 reserved1;
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u32 vlan_etype_cfg;
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u32 port_mode[12];
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u32 front_port_mode[10];
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u32 frame_aging;
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u32 stat_cfg;
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u32 reserved2[50];
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};
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struct vsc9953_sys_pause_cfg {
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u32 pause_cfg[11];
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u32 pause_tot_cfg;
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u32 tail_drop_level[11];
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u32 tot_tail_drop_lvl;
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u32 mac_fc_cfg[10];
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};
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struct vsc9953_sys_mmgt {
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u16 free_cnt;
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};
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struct vsc9953_system_reg {
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struct vsc9953_sys_stat stat;
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struct vsc9953_sys_sys sys;
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struct vsc9953_sys_pause_cfg pause_cfg;
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struct vsc9953_sys_mmgt mmgt;
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};
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/* END VSC9953 SYS structure */
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/* VSC9953 REW structure */
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struct vsc9953_rew_port {
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u32 port_vlan_cfg;
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u32 port_tag_cfg;
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u32 port_port_cfg;
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u32 port_dscp_cfg;
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u32 port_pcp_dei_qos_map_cfg[16];
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u32 reserved[12];
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};
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|
struct vsc9953_rew_common {
|
u32 reserve[4];
|
u32 dscp_remap_dp1_cfg[64];
|
u32 dscp_remap_cfg[64];
|
};
|
|
struct vsc9953_rew_reg {
|
struct vsc9953_rew_port port[12];
|
struct vsc9953_rew_common common;
|
};
|
|
/* END VSC9953 REW structure */
|
|
/* VSC9953 DEVCPU_GCB structure */
|
|
struct vsc9953_chip_regs {
|
u32 chipd_id;
|
u32 gpr;
|
u32 soft_rst;
|
};
|
|
struct vsc9953_gpio {
|
u32 gpio_out_set[10];
|
u32 gpio_out_clr[10];
|
u32 gpio_out[10];
|
u32 gpio_in[10];
|
};
|
|
struct vsc9953_mii_mng {
|
u32 miimstatus;
|
u32 reserved1;
|
u32 miimcmd;
|
u32 miimdata;
|
u32 miimcfg;
|
u32 miimscan_0;
|
u32 miimscan_1;
|
u32 miiscan_lst_rslts;
|
u32 miiscan_lst_rslts_valid;
|
};
|
|
struct vsc9953_mii_read_scan {
|
u32 mii_scan_results_sticky[2];
|
};
|
|
struct vsc9953_devcpu_gcb {
|
struct vsc9953_chip_regs chip_regs;
|
struct vsc9953_gpio gpio;
|
struct vsc9953_mii_mng mii_mng[2];
|
struct vsc9953_mii_read_scan mii_read_scan;
|
};
|
|
/* END VSC9953 DEVCPU_GCB structure */
|
|
/* VSC9953 IS* structure */
|
|
struct vsc9953_vcap_core_cfg {
|
u32 vcap_update_ctrl;
|
u32 vcap_mv_cfg;
|
};
|
|
struct vsc9953_vcap {
|
struct vsc9953_vcap_core_cfg vcap_core_cfg;
|
};
|
|
/* END VSC9953 IS* structure */
|
|
#define VSC9953_PORT_INFO_INITIALIZER(idx) \
|
{ \
|
.enabled = 0, \
|
.phyaddr = 0, \
|
.index = idx, \
|
.phy_regs = NULL, \
|
.enet_if = PHY_INTERFACE_MODE_NONE, \
|
.bus = NULL, \
|
.phydev = NULL, \
|
}
|
|
/* Structure to describe a VSC9953 port */
|
struct vsc9953_port_info {
|
u8 enabled;
|
u8 phyaddr;
|
int index;
|
void *phy_regs;
|
phy_interface_t enet_if;
|
struct mii_dev *bus;
|
struct phy_device *phydev;
|
};
|
|
/* Structure to describe a VSC9953 switch */
|
struct vsc9953_info {
|
struct vsc9953_port_info port[VSC9953_MAX_PORTS];
|
};
|
|
void vsc9953_init(bd_t *bis);
|
|
void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
|
void vsc9953_port_info_set_phy_address(int port_no, int address);
|
void vsc9953_port_enable(int port_no);
|
void vsc9953_port_disable(int port_no);
|
void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
|
|
#endif /* _VSC9953_H_ */
|
