/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _VIRTEX2_H_
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#define _VIRTEX2_H_
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#include <xilinx.h>
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/*
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* Slave SelectMap Implementation function table.
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*/
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typedef struct {
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xilinx_pre_fn pre;
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xilinx_pgm_fn pgm;
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xilinx_init_fn init;
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xilinx_err_fn err;
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xilinx_done_fn done;
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xilinx_clk_fn clk;
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xilinx_cs_fn cs;
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xilinx_wr_fn wr;
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xilinx_rdata_fn rdata;
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xilinx_wdata_fn wdata;
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xilinx_busy_fn busy;
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xilinx_abort_fn abort;
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xilinx_post_fn post;
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} xilinx_virtex2_slave_selectmap_fns;
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/* Slave Serial Implementation function table */
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typedef struct {
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xilinx_pgm_fn pgm;
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xilinx_clk_fn clk;
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xilinx_rdata_fn rdata;
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xilinx_wdata_fn wdata;
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} xilinx_virtex2_slave_serial_fns;
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#if defined(CONFIG_FPGA_VIRTEX2)
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extern struct xilinx_fpga_op virtex2_op;
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# define FPGA_VIRTEX2_OPS &virtex2_op
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#else
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# define FPGA_VIRTEX2_OPS NULL
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#endif
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/* Device Image Sizes (in bytes)
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*********************************************************************/
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#define XILINX_XC2V40_SIZE (338208 / 8)
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#define XILINX_XC2V80_SIZE (597408 / 8)
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#define XILINX_XC2V250_SIZE (1591584 / 8)
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#define XILINX_XC2V500_SIZE (2557857 / 8)
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#define XILINX_XC2V1000_SIZE (3749408 / 8)
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#define XILINX_XC2V1500_SIZE (5166240 / 8)
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#define XILINX_XC2V2000_SIZE (6808352 / 8)
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#define XILINX_XC2V3000_SIZE (9589408 / 8)
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#define XILINX_XC2V4000_SIZE (14220192 / 8)
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#define XILINX_XC2V6000_SIZE (19752096 / 8)
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#define XILINX_XC2V8000_SIZE (26185120 / 8)
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#define XILINX_XC2V10000_SIZE (33519264 / 8)
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/* Descriptor Macros
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*********************************************************************/
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#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#endif /* _VIRTEX2_H_ */
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