/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2022 Rockchip Electronics Co., Ltd
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*/
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#ifndef _MAX96755F_H_
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#define _MAX96755F_H_
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#include <linux/bitfield.h>
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#include <asm-generic/gpio.h>
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#include <drm_modes.h>
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#define GPIO_A_REG(gpio) (0x02be + ((gpio) * 3))
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#define GPIO_B_REG(gpio) (0x02bf + ((gpio) * 3))
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#define GPIO_C_REG(gpio) (0x02c0 + ((gpio) * 3))
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/* 0000h */
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#define DEV_ADDR GENMASK(7, 1)
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#define CFG_BLOCK BIT(0)
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/* 0001h */
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#define IIC_2_EN BIT(7)
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#define IIC_1_EN BIT(6)
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#define DIS_REM_CC BIT(4)
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#define TX_RATE GENMASK(3, 2)
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/* 0002h */
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#define VID_TX_EN_U BIT(7)
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#define VID_TX_EN_Z BIT(6)
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#define VID_TX_EN_Y BIT(5)
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#define VID_TX_EN_X BIT(4)
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#define AUD_TX_EN_Y BIT(3)
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#define AUD_TX_EN_X BIT(2)
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/* 0003h */
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#define UART_2_EN BIT(5)
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#define UART_1_EN BIT(4)
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/* 0005h */
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#define LOCK_EN BIT(7)
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#define ERRB_EN BIT(6)
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#define PU_LF3 BIT(3)
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#define PU_LF2 BIT(2)
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#define PU_LF1 BIT(1)
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#define PU_LF0 BIT(0)
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/* 0006h */
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#define RCLKEN BIT(5)
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/* 0010h */
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#define RESET_ALL BIT(7)
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#define RESET_LINK BIT(6)
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#define RESET_ONESHOT BIT(5)
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#define AUTO_LINK BIT(4)
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#define SLEEP BIT(3)
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#define REG_ENABLE BIT(2)
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#define LINK_CFG GENMASK(1, 0)
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/* 0013h */
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#define LINK_MODE GENMASK(5, 4)
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#define LOCKED BIT(3)
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/* 0048h */
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#define REM_MS_EN BIT(5)
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#define LOC_MS_EN BIT(4)
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/* 0053h */
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#define TX_SPLIT_MASK_B BIT(5)
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#define TX_SPLIT_MASK_A BIT(4)
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#define TX_STR_SEL GENMASK(1, 0)
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/* 0140h */
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#define AUD_RX_EN BIT(0)
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/* 0170h */
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#define SPI_EN BIT(0)
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/* 02beh */
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#define RES_CFG BIT(7)
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#define TX_PRIO BIT(6)
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#define TX_COMP_EN BIT(5)
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#define GPIO_OUT BIT(4)
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#define GPIO_IN BIT(3)
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#define GPIO_RX_EN BIT(2)
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#define GPIO_TX_EN BIT(1)
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#define GPIO_OUT_DIS BIT(0)
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/* 02bfh */
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#define PULL_UPDN_SEL GENMASK(7, 6)
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#define OUT_TYPE BIT(5)
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#define GPIO_TX_ID GENMASK(4, 0)
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/* 02c0h */
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#define OVR_RES_CFG BIT(7)
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#define GPIO_RX_ID GENMASK(4, 0)
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/* 0311h */
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#define START_PORTBU BIT(7)
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#define START_PORTBZ BIT(6)
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#define START_PORTBY BIT(5)
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#define START_PORTBX BIT(4)
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#define START_PORTAU BIT(3)
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#define START_PORTAZ BIT(2)
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#define START_PORTAY BIT(1)
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#define START_PORTAX BIT(0)
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/* 032ah */
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#define DV_LOCK BIT(7)
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#define DV_SWP_AB BIT(6)
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#define LINE_ALT BIT(5)
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#define DV_CONV BIT(2)
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#define DV_SPL BIT(1)
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#define DV_EN BIT(0)
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/* 0330h */
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#define PHY_CONFIG GENMASK(2, 0)
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#define MIPI_RX_RESET BIT(3)
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/* 0331h */
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#define NUM_LANES GENMASK(1, 0)
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/* 0385h */
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#define DPI_HSYNC_WIDTH_L GENMASK(7, 0)
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/* 0386h */
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#define DPI_VYSNC_WIDTH_L GENMASK(7, 0)
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/* 0387h */
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#define DPI_HSYNC_WIDTH_H GENMASK(3, 0)
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#define DPI_VSYNC_WIDTH_H GENMASK(7, 4)
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/* 03a4h */
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#define DPI_DE_SKEW_SEL BIT(1)
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#define DPI_DESKEW_EN BIT(0)
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/* 03a5h */
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#define DPI_VFP_L GENMASK(7, 0)
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/* 03a6h */
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#define DPI_VFP_H GENMASK(3, 0)
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#define DPI_VBP_L GENMASK(7, 4)
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/* 03a7h */
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#define DPI_VBP_H GENMASK(7, 0)
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/* 03a8h */
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#define DPI_VACT_L GENMASK(7, 0)
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/* 03a9h */
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#define DPI_VACT_H GENMASK(3, 0)
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/* 03aah */
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#define DPI_HFP_L GENMASK(7, 0)
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/* 03abh */
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#define DPI_HFP_H GENMASK(3, 0)
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#define DPI_HBP_L GENMASK(7, 4)
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/* 03ach */
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#define DPI_HBP_H GENMASK(7, 0)
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/* 03adh */
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#define DPI_HACT_L GENMASK(7, 0)
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/* 03aeh */
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#define DPI_HACT_H GENMASK(4, 0)
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enum link_mode {
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DUAL_LINK,
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LINKA,
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LINKB,
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SPLITTER_MODE,
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};
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struct max96755f_priv {
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struct udevice *dev;
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struct gpio_desc enable_gpio;
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bool split_mode;
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bool dv_swp_ab;
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bool dpi_deskew_en;
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struct drm_display_mode mode;
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u32 num_lanes;
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};
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#endif
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