/*
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* Copyright (c) 2015, NVIDIA CORPORATION.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ABI_MACH_T186_RESET_T186_H_
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#define _ABI_MACH_T186_RESET_T186_H_
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#define TEGRA186_RESET_ACTMON 0
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#define TEGRA186_RESET_AFI 1
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#define TEGRA186_RESET_CEC 2
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#define TEGRA186_RESET_CSITE 3
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#define TEGRA186_RESET_DP2 4
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#define TEGRA186_RESET_DPAUX 5
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#define TEGRA186_RESET_DSI 6
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#define TEGRA186_RESET_DSIB 7
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#define TEGRA186_RESET_DTV 8
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#define TEGRA186_RESET_DVFS 9
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#define TEGRA186_RESET_ENTROPY 10
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#define TEGRA186_RESET_EXTPERIPH1 11
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#define TEGRA186_RESET_EXTPERIPH2 12
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#define TEGRA186_RESET_EXTPERIPH3 13
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#define TEGRA186_RESET_GPU 14
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#define TEGRA186_RESET_HDA 15
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#define TEGRA186_RESET_HDA2CODEC_2X 16
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#define TEGRA186_RESET_HDA2HDMICODEC 17
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#define TEGRA186_RESET_HOST1X 18
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#define TEGRA186_RESET_I2C1 19
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#define TEGRA186_RESET_I2C2 20
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#define TEGRA186_RESET_I2C3 21
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#define TEGRA186_RESET_I2C4 22
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#define TEGRA186_RESET_I2C5 23
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#define TEGRA186_RESET_I2C6 24
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#define TEGRA186_RESET_ISP 25
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#define TEGRA186_RESET_KFUSE 26
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#define TEGRA186_RESET_LA 27
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#define TEGRA186_RESET_MIPI_CAL 28
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#define TEGRA186_RESET_PCIE 29
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#define TEGRA186_RESET_PCIEXCLK 30
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#define TEGRA186_RESET_SATA 31
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#define TEGRA186_RESET_SATACOLD 32
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#define TEGRA186_RESET_SDMMC1 33
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#define TEGRA186_RESET_SDMMC2 34
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#define TEGRA186_RESET_SDMMC3 35
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#define TEGRA186_RESET_SDMMC4 36
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#define TEGRA186_RESET_SE 37
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#define TEGRA186_RESET_SOC_THERM 38
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#define TEGRA186_RESET_SOR0 39
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#define TEGRA186_RESET_SPI1 40
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#define TEGRA186_RESET_SPI2 41
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#define TEGRA186_RESET_SPI3 42
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#define TEGRA186_RESET_SPI4 43
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#define TEGRA186_RESET_TMR 44
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#define TEGRA186_RESET_TRIG_SYS 45
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#define TEGRA186_RESET_TSEC 46
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#define TEGRA186_RESET_UARTA 47
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#define TEGRA186_RESET_UARTB 48
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#define TEGRA186_RESET_UARTC 49
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#define TEGRA186_RESET_UARTD 50
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#define TEGRA186_RESET_VI 51
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#define TEGRA186_RESET_VIC 52
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#define TEGRA186_RESET_XUSB_DEV 53
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#define TEGRA186_RESET_XUSB_HOST 54
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#define TEGRA186_RESET_XUSB_PADCTL 55
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#define TEGRA186_RESET_XUSB_SS 56
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#define TEGRA186_RESET_AON_APB 57
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#define TEGRA186_RESET_AXI_CBB 58
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#define TEGRA186_RESET_BPMP_APB 59
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#define TEGRA186_RESET_CAN1 60
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#define TEGRA186_RESET_CAN2 61
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#define TEGRA186_RESET_DMIC5 62
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#define TEGRA186_RESET_DSIC 63
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#define TEGRA186_RESET_DSID 64
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#define TEGRA186_RESET_EMC_EMC 65
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#define TEGRA186_RESET_EMC_MEM 66
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#define TEGRA186_RESET_EMCSB_EMC 67
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#define TEGRA186_RESET_EMCSB_MEM 68
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#define TEGRA186_RESET_EQOS 69
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#define TEGRA186_RESET_GPCDMA 70
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#define TEGRA186_RESET_GPIO_CTL0 71
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#define TEGRA186_RESET_GPIO_CTL1 72
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#define TEGRA186_RESET_GPIO_CTL2 73
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#define TEGRA186_RESET_GPIO_CTL3 74
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#define TEGRA186_RESET_GPIO_CTL4 75
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#define TEGRA186_RESET_GPIO_CTL5 76
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#define TEGRA186_RESET_I2C10 77
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#define TEGRA186_RESET_I2C12 78
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#define TEGRA186_RESET_I2C13 79
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#define TEGRA186_RESET_I2C14 80
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#define TEGRA186_RESET_I2C7 81
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#define TEGRA186_RESET_I2C8 82
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#define TEGRA186_RESET_I2C9 83
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#define TEGRA186_RESET_JTAG2AXI 84
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#define TEGRA186_RESET_MPHY_IOBIST 85
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#define TEGRA186_RESET_MPHY_L0_RX 86
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#define TEGRA186_RESET_MPHY_L0_TX 87
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#define TEGRA186_RESET_NVCSI 88
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#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89
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#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90
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#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91
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#define TEGRA186_RESET_NVDISPLAY0_MISC 92
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#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93
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#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94
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#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95
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#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96
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#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97
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#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98
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#define TEGRA186_RESET_PWM1 99
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#define TEGRA186_RESET_PWM2 100
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#define TEGRA186_RESET_PWM3 101
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#define TEGRA186_RESET_PWM4 102
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#define TEGRA186_RESET_PWM5 103
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#define TEGRA186_RESET_PWM6 104
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#define TEGRA186_RESET_PWM7 105
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#define TEGRA186_RESET_PWM8 106
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#define TEGRA186_RESET_SCE_APB 107
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#define TEGRA186_RESET_SOR1 108
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#define TEGRA186_RESET_TACH 109
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#define TEGRA186_RESET_TSC 110
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#define TEGRA186_RESET_UARTF 111
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#define TEGRA186_RESET_UARTG 112
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#define TEGRA186_RESET_UFSHC 113
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#define TEGRA186_RESET_UFSHC_AXI_M 114
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#define TEGRA186_RESET_UPHY 115
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#define TEGRA186_RESET_ADSP 116
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#define TEGRA186_RESET_ADSPDBG 117
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#define TEGRA186_RESET_ADSPINTF 118
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#define TEGRA186_RESET_ADSPNEON 119
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#define TEGRA186_RESET_ADSPPERIPH 120
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#define TEGRA186_RESET_ADSPSCU 121
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#define TEGRA186_RESET_ADSPWDT 122
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#define TEGRA186_RESET_APE 123
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#define TEGRA186_RESET_DPAUX1 124
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#define TEGRA186_RESET_NVDEC 125
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#define TEGRA186_RESET_NVENC 126
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#define TEGRA186_RESET_NVJPG 127
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#define TEGRA186_RESET_PEX_USB_UPHY 128
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#define TEGRA186_RESET_QSPI 129
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#define TEGRA186_RESET_TSECB 130
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#define TEGRA186_RESET_VI_I2C 131
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#define TEGRA186_RESET_UARTE 132
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#define TEGRA186_RESET_TOP_GTE 133
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#define TEGRA186_RESET_SHSP 134
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#define TEGRA186_RESET_PEX_USB_UPHY_L5 135
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#define TEGRA186_RESET_PEX_USB_UPHY_L4 136
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#define TEGRA186_RESET_PEX_USB_UPHY_L3 137
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#define TEGRA186_RESET_PEX_USB_UPHY_L2 138
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#define TEGRA186_RESET_PEX_USB_UPHY_L1 139
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#define TEGRA186_RESET_PEX_USB_UPHY_L0 140
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#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141
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#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142
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#define TEGRA186_RESET_TSCTNVI 143
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#define TEGRA186_RESET_EXTPERIPH4 144
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#define TEGRA186_RESET_DSIPADCTL 145
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#define TEGRA186_RESET_AUD_MCLK 146
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#define TEGRA186_RESET_MPHY_CLK_CTL 147
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#define TEGRA186_RESET_MPHY_L1_RX 148
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#define TEGRA186_RESET_MPHY_L1_TX 149
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#define TEGRA186_RESET_UFSHC_LP 150
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#define TEGRA186_RESET_BPMP_NIC 151
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#define TEGRA186_RESET_BPMP_NSYSPORESET 152
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#define TEGRA186_RESET_BPMP_NRESET 153
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#define TEGRA186_RESET_BPMP_DBGRESETN 154
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#define TEGRA186_RESET_BPMP_PRESETDBGN 155
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#define TEGRA186_RESET_BPMP_PM 156
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#define TEGRA186_RESET_BPMP_CVC 157
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#define TEGRA186_RESET_BPMP_DMA 158
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#define TEGRA186_RESET_BPMP_HSP 159
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#define TEGRA186_RESET_TSCTNBPMP 160
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#define TEGRA186_RESET_BPMP_TKE 161
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#define TEGRA186_RESET_BPMP_GTE 162
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#define TEGRA186_RESET_BPMP_PM_ACTMON 163
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#define TEGRA186_RESET_AON_NIC 164
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#define TEGRA186_RESET_AON_NSYSPORESET 165
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#define TEGRA186_RESET_AON_NRESET 166
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#define TEGRA186_RESET_AON_DBGRESETN 167
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#define TEGRA186_RESET_AON_PRESETDBGN 168
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#define TEGRA186_RESET_AON_ACTMON 169
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#define TEGRA186_RESET_AOPM 170
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#define TEGRA186_RESET_AOVC 171
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#define TEGRA186_RESET_AON_DMA 172
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#define TEGRA186_RESET_AON_GPIO 173
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#define TEGRA186_RESET_AON_HSP 174
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#define TEGRA186_RESET_TSCTNAON 175
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#define TEGRA186_RESET_AON_TKE 176
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#define TEGRA186_RESET_AON_GTE 177
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#define TEGRA186_RESET_SCE_NIC 178
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#define TEGRA186_RESET_SCE_NSYSPORESET 179
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#define TEGRA186_RESET_SCE_NRESET 180
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#define TEGRA186_RESET_SCE_DBGRESETN 181
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#define TEGRA186_RESET_SCE_PRESETDBGN 182
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#define TEGRA186_RESET_SCE_ACTMON 183
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#define TEGRA186_RESET_SCE_PM 184
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#define TEGRA186_RESET_SCE_DMA 185
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#define TEGRA186_RESET_SCE_HSP 186
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#define TEGRA186_RESET_TSCTNSCE 187
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#define TEGRA186_RESET_SCE_TKE 188
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#define TEGRA186_RESET_SCE_GTE 189
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#define TEGRA186_RESET_SCE_CFG 190
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#define TEGRA186_RESET_ADSP_ALL 191
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/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */
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#define TEGRA186_RESET_UFSHC_LP_SEQ 192
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#define TEGRA186_RESET_SIZE 193
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#endif
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