/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __FLASH_H
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#define __FLASH_H
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#ifndef BIT
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#define BIT(nr) (1 << (nr))
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#endif
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#define MAX_FLASH_NUM 2
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#define MAX_IDB_RESERVED_BLOCK 12
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#define NAND_CACHE_READ_EN BIT(0)
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#define NAND_CACHE_RANDOM_READ_EN BIT(1)
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#define NAND_CACHE_PROG_EN BIT(2)
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#define NAND_MULTI_READ_EN BIT(3)
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#define NAND_MULTI_PROG_EN BIT(4)
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#define NAND_INTERLEAVE_EN BIT(5)
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#define NAND_READ_RETRY_EN BIT(6)
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#define NAND_RANDOMIZER_EN BIT(7)
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#define NAND_INTER_MODE_OFFSET (0x8)
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#define NAND_INTER_MODE_MARK (0x07)
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#define NAND_INTER_SDR_EN BIT(0)
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#define NAND_INTER_ONFI_EN BIT(1)
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#define NAND_INTER_TOGGLE_EN BIT(2)
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#define NAND_SDR_EN BIT(8)
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#define NAND_ONFI_EN BIT(9)
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#define NAND_TOGGLE_EN BIT(10)
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#define NAND_UNIQUE_ID_EN BIT(11)
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#define RESET_CMD 0xff
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#define READ_ID_CMD 0x90
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#define READ_STATUS_CMD 0x70
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#define PAGE_PROG_CMD 0x8010
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#define BLOCK_ERASE_CMD 0x60d0
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#define READ_CMD 0x0030
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#define READ_DP_OUT_CMD 0x05E0
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#define READ_ECC_STATUS_CMD 0x7A
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#define SAMSUNG 0x00 /* SAMSUNG */
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#define TOSHIBA 0x01 /* TOSHIBA */
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#define HYNIX 0x02 /* HYNIX */
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#define INFINEON 0x03 /* INFINEON */
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#define MICRON 0x04 /* MICRON */
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#define RENESAS 0x05 /* RENESAS */
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#define ST 0x06 /* ST */
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#define INTEL 0x07 /* intel */
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#define Sandisk 0x08 /* Sandisk */
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#define RR_NONE 0x00
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#define RR_HY_1 0x01 /* hynix H27UCG8T2M */
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#define RR_HY_2 0x02 /* hynix H27UBG08U0B */
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#define RR_HY_3 0x03 /* hynix H27UCG08U0B H27UBG08U0C */
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#define RR_HY_4 0x04 /* hynix H27UCG8T2A */
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#define RR_HY_5 0x05 /* hynix H27UCG8T2E */
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#define RR_HY_6 0x06 /* hynix H27QCG8T2F5R-BCG */
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#define RR_MT_1 0x11 /* micron */
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#define RR_MT_2 0x12 /* micron L94C L95B */
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#define RR_TH_1 0x21 /* toshiba */
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#define RR_TH_2 0x22 /* toshiba */
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#define RR_TH_3 0x23 /* toshiba */
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#define RR_SS_1 0x31 /* samsung */
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#define RR_SD_1 0x41 /* Sandisk */
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#define RR_SD_2 0x42 /* Sandisk */
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#define RR_SD_3 0x43 /* Sandisk */
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#define RR_SD_4 0x44 /* Sandisk */
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/* 0 1 2 3 4 5 6 7 8 9 slc */
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#define LSB_0 0
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/* 0 1 2 3 6 7 A B E F hynix, micron 74A */
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#define LSB_1 1
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/* 0 1 3 5 7 9 B D toshiba samsung sandisk */
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#define LSB_2 2
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/* 0 1 2 3 4 5 8 9 C D 10 11 micron 84A */
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#define LSB_3 3
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/* 0 1 2 3 4 5 7 8 A B E F micron L95B */
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#define LSB_4 4
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/* 0 1 2 3 4 5 8 9 14 15 20 21 26 27 micron B74A TLC */
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#define LSB_6 6
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/* 0 3 6 9 C F 12 15 18 15 1B 1E 21 24 K9ABGD8U0C TLC */
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#define LSB_7 7
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/* BadBlockFlagMode */
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/* first spare @ first page of each blocks */
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#define BBF_1 1
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/* first spare @ last page of each blocks */
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#define BBF_2 2
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/* first spare @ first and last page of each blocks */
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#define BBF_11 3
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/* sandisk 15nm flash prog first page without data and check status */
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#define BBF_3 4
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#define MPM_0 0 /* block 0 ~ 1 */
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#define MPM_1 1 /* block 0 ~ 2048... */
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struct NAND_PARA_INFO_T {
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u8 id_bytes;
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u8 nand_id[6];
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u8 vendor;
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u8 die_per_chip;
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u8 sec_per_page;
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u16 page_per_blk;
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u8 cell; /* 1 slc , 2 mlc , 3 tlc */
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u8 plane_per_die;
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u16 blk_per_plane;
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u16 operation_opt;
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u8 lsb_mode;
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u8 read_retry_mode;
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u8 ecc_bits;
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u8 access_freq;
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u8 opt_mode;
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u8 die_gap;
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u8 bad_block_mode;
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u8 multi_plane_mode;
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u8 reversd2[6]; /* 32 bytes */
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};
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extern struct nand_phy_info g_nand_phy_info;
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extern struct nand_ops g_nand_ops;
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extern void __iomem *nandc_base;
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void nandc_flash_get_id(u8 cs, void *buf);
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void nandc_flash_reset(u8 chip_sel);
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u32 nandc_flash_init(void __iomem *nandc_addr);
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u32 nandc_flash_deinit(void);
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#endif
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