// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <power/regulator.h>
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#include "ddr_tester_common.h"
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DECLARE_GLOBAL_DATA_PTR;
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void write_buf_to_ddr(u32 *buf, u32 buf_len, ulong start_adr, ulong length)
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{
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ulong *buful = (ulong *)buf;
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ulong *p = (ulong *)start_adr;
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u32 i, j;
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buf_len = buf_len / sizeof(ulong) - 1;
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for (i = 0, j = 0; i < length / sizeof(p[0]); i++) {
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p[i] = buful[j];
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j++;
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j &= buf_len;
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}
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}
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ulong cmp_buf_data(u32 *buf, u32 buf_len, ulong start_adr, ulong length,
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u32 prt_en)
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{
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ulong *buful = (ulong *)buf;
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volatile unsigned long *p = (volatile unsigned long *)start_adr;
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u32 i, j;
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ulong reread = 0;
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ulong wr_val = 0;
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ulong val = 0;
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ulong err_adr = 0;
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buf_len = buf_len / sizeof(ulong) - 1;
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err_adr = 0;
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for (i = 0, j = 0; i < length / sizeof(p[0]); i++) {
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val = p[i];
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if (val != buful[j]) {
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flush_dcache_range((ulong)&p[i],
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(ulong)&p[i] + sizeof(u32));
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reread = p[i];
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err_adr = (ulong)&p[i];
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wr_val = buful[j];
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break;
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}
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j++;
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j &= buf_len;
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}
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if (err_adr && prt_en)
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printf("test fail:address:0x%lx,read:0x%lx,"
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"reread:0x%lx,expect:0x%lx\n",
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err_adr, val, reread, wr_val);
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return err_adr;
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}
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void print_memory(void *addr, ulong size)
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{
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u32 *p = addr;
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u32 i;
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for (i = 0; i < size / 4; i += 4) {
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printf("0x%08lx: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
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(ulong)&p[i], p[i], p[i + 1], p[i + 2], p[i + 3]);
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}
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}
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/* print available address for ddr testing in uboot */
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void get_print_available_addr(ulong *start_adr, ulong *length, int print_en)
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{
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u32 i, max_bank = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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if (gd->bd->bi_dram[i].start)
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max_bank = i + 1;
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start_adr[i] = 0;
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length[i] = 0;
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}
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for (i = 0; i < max_bank; i++) {
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start_adr[i] = gd->bd->bi_dram[i].start;
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length[i] = gd->bd->bi_dram[i].size;
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}
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length[max_bank - 1] = (gd->start_addr_sp - RESERVED_SP_SIZE -
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start_adr[max_bank - 1]) & ~0xfff;
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if (print_en) {
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printf("available memory for test:\n");
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printf(" start end length\n");
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for (i = 0; i < max_bank; i++)
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if (length[i])
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printf(" 0x%08lx - 0x%08lx 0x%08lx\n",
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start_adr[i], start_adr[i] + length[i],
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length[i]);
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}
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}
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/*
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* judge if testing address is available
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* arg[0]:start addr, arg[1]:length, return test banks number
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*/
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int judge_test_addr(ulong *arg, ulong *start_adr, ulong *length)
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{
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u32 i, max_bank = 0;
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u32 available = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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if (start_adr[i])
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max_bank = i + 1;
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if (!arg[1])
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return max_bank;
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for (i = 0; i < max_bank; i++)
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if (arg[0] >= start_adr[i] &&
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arg[0] + arg[1] <= start_adr[i] + length[i])
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available |= 1;
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if (!available) {
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printf("Invalid test address\n");
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} else {
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start_adr[0] = arg[0];
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length[0] = arg[1];
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for (i = 1; i < max_bank; i++) {
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start_adr[i] = 0;
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length[i] = 0;
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}
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}
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return available;
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}
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int set_vdd_logic(u32 uv)
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{
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struct udevice *dev;
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int ret;
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ret = regulator_get_by_platname("vdd_logic", &dev);
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if (ret) {
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printf("Cannot set regulator name\n");
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return ret;
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}
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/* Slowly raise to max CPU voltage to prevent overshoot */
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ret = regulator_set_value(dev, uv);
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udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
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if (ret)
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printf("set vdd_logic fail\n");
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return ret;
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}
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