/*
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* (C) Copyright 2012-2013, Xilinx, Michal Simek
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*
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* (C) Copyright 2012
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* Joe Hershberger <joe.hershberger@ni.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ZYNQPL_H_
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#define _ZYNQPL_H_
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#include <xilinx.h>
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#if defined(CONFIG_FPGA_ZYNQPL)
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extern struct xilinx_fpga_op zynq_op;
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# define FPGA_ZYNQPL_OPS &zynq_op
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#else
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# define FPGA_ZYNQPL_OPS NULL
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#endif
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#define XILINX_ZYNQ_7007S 0x3
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#define XILINX_ZYNQ_7010 0x2
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#define XILINX_ZYNQ_7012S 0x1c
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#define XILINX_ZYNQ_7014S 0x8
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#define XILINX_ZYNQ_7015 0x1b
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#define XILINX_ZYNQ_7020 0x7
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#define XILINX_ZYNQ_7030 0xc
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#define XILINX_ZYNQ_7035 0x12
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#define XILINX_ZYNQ_7045 0x11
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#define XILINX_ZYNQ_7100 0x16
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/* Device Image Sizes */
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#define XILINX_XC7Z007S_SIZE 16669920/8
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#define XILINX_XC7Z010_SIZE 16669920/8
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#define XILINX_XC7Z012S_SIZE 28085344/8
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#define XILINX_XC7Z014S_SIZE 32364512/8
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#define XILINX_XC7Z015_SIZE 28085344/8
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#define XILINX_XC7Z020_SIZE 32364512/8
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#define XILINX_XC7Z030_SIZE 47839328/8
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#define XILINX_XC7Z035_SIZE 106571232/8
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#define XILINX_XC7Z045_SIZE 106571232/8
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#define XILINX_XC7Z100_SIZE 139330784/8
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/* Descriptor Macros */
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#define XILINX_XC7Z007S_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z007s" }
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#define XILINX_XC7Z010_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z010" }
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#define XILINX_XC7Z012S_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z012s" }
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#define XILINX_XC7Z014S_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z014s" }
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#define XILINX_XC7Z015_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z015" }
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#define XILINX_XC7Z020_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z020" }
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#define XILINX_XC7Z030_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z030" }
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#define XILINX_XC7Z035_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z035" }
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#define XILINX_XC7Z045_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z045" }
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#define XILINX_XC7Z100_DESC(cookie) \
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{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z100" }
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#endif /* _ZYNQPL_H_ */
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