/*
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* Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
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*
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* Copyright (C) 2010 Andes Technology Corporation
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* Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FTPCI100_H
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#define __FTPCI100_H
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/* AHB Control Registers */
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struct ftpci100_ahbc {
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unsigned int iosize; /* 0x00 - I/O Space Size Signal */
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unsigned int prot; /* 0x04 - AHB Protection */
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unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
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unsigned int conf; /* 0x28 - PCI Configuration */
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unsigned int data; /* 0x2c - PCI Configuration DATA */
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};
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/*
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* FTPCI100_IOSIZE_REG's constant definitions
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*/
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#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */
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/*
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* PCI Configuration Register
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*/
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#define PCI_INT_MASK 0x4c
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#define PCI_MEM_BASE_SIZE1 0x50
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#define PCI_MEM_BASE_SIZE2 0x54
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#define PCI_MEM_BASE_SIZE3 0x58
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/*
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* PCI_INT_MASK's bit definitions
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*/
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#define PCI_INTA_ENABLE (1 << 22)
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#define PCI_INTB_ENABLE (1 << 23)
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#define PCI_INTC_ENABLE (1 << 24)
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#define PCI_INTD_ENABLE (1 << 25)
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/*
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* PCI_MEM_BASE_SIZE1's constant definitions
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*/
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#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */
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#define FTPCI100_MAX_FUNCTIONS 20
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#define PCI_IRQ_LINES 4
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#define MAX_BUS_NUM 256
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#define MAX_DEV_NUM 32
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#define MAX_FUN_NUM 8
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#define PCI_MAX_BAR_PER_FUNC 6
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/*
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* PCI_MEM_SIZE
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*/
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#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24)
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/* This definition is used by pci_ftpci_init() */
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#define FTPCI100_BRIDGE_VENDORID 0x159b
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#define FTPCI100_BRIDGE_DEVICEID 0x4321
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void pci_ftpci_init(void);
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struct pcibar {
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unsigned int size;
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unsigned int addr;
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};
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struct pci_config {
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unsigned int bus;
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unsigned int dev; /* device */
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unsigned int func;
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unsigned int pin;
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unsigned short v_id; /* vendor id */
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unsigned short d_id; /* device id */
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struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];
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};
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#endif
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